公开(公告)号：US20210183810A1

公开(公告)日：2021-06-17

申请号：US17189324

申请日：2021-03-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT

IPC: H01L23/00

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

公开(公告)号：US20220319871A1

公开(公告)日：2022-10-06

申请号：US17843938

申请日：2022-06-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  BRETT P. WILKERSON ,  LEI FU ,  RAHUL AGARWAL

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US20230201952A1

公开(公告)日：2023-06-29

申请号：US17563830

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  BRETT P. WILKERSON

IPC: B23K20/02 ,  B23K20/24

CPC classification number: B23K20/02 ,  B23K20/24 ,  B23K2101/40

Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

公开(公告)号：US20220199429A1

公开(公告)日：2022-06-23

申请号：US17554498

申请日：2021-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  RAJA SWAMINATHAN ,  BRETT P. WILKERSON

IPC: H01L21/48 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  H01L23/42 ,  H01L21/56

Abstract: Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.

公开(公告)号：US20210193604A1

公开(公告)日：2021-06-24

申请号：US17195046

申请日：2021-03-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  LEI FU

IPC: H01L23/00

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.