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    SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS
    1.
    发明申请
    SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS 有权

    公开(公告)号：US20210193604A1

    公开(公告)日：2021-06-24

    申请号：US17195046

    申请日：2021-03-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  LEI FU

    IPC: H01L23/00

    Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

    INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR
    2.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR 有权

    公开(公告)号：US20210313269A1

    公开(公告)日：2021-10-07

    申请号：US17323454

    申请日：2021-05-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： MILIND S. BHAGAVAT ,  RAHUL AGARWAL ,  CHIA-HAO CHENG

    IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

    BOND PADS FOR LOW TEMPERATURE HYBRID BONDING
    3.
    发明申请
    BOND PADS FOR LOW TEMPERATURE HYBRID BONDING 有权

    公开(公告)号：US20210183810A1

    公开(公告)日：2021-06-17

    申请号：US17189324

    申请日：2021-03-02

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT

    IPC: H01L23/00

    Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

    MULTIROW SEMICONDUCTOR CHIP CONNECTIONS
    5.
    发明申请
    MULTIROW SEMICONDUCTOR CHIP CONNECTIONS 有权

    公开(公告)号：US20220189879A1

    公开(公告)日：2022-06-16

    申请号：US17122571

    申请日：2020-12-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RAHUL AGARWAL ,  MILIND S. BHAGAVAT

    IPC: H01L23/538 ,  H01L23/00

    Abstract: A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.

    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES
    7.
    发明申请
    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES 有权

    公开(公告)号：US20220319871A1

    公开(公告)日：2022-10-06

    申请号：US17843938

    申请日：2022-06-17

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  BRETT P. WILKERSON ,  LEI FU ,  RAHUL AGARWAL

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

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