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    FANOUT MODULE INTEGRATING A PHOTONIC INTEGRATED CIRCUIT
    4.
    发明公开
    FANOUT MODULE INTEGRATING A PHOTONIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240019649A1

    公开(公告)日：2024-01-18

    申请号：US18357376

    申请日：2023-07-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： BRETT P. WILKERSON ,  RAJA SWAMINATHAN ,  KONG TOON NG ,  RAHUL AGARWAL

    IPC: G02B6/42

    CPC classification number: G02B6/4274 ,  G02B6/4255 ,  G02B6/425 ,  G02B6/43

    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

    LOW TEMPERATURE HYBRID BONDING
    5.
    发明公开
    LOW TEMPERATURE HYBRID BONDING 审中-公开

    公开(公告)号：US20230201952A1

    公开(公告)日：2023-06-29

    申请号：US17563830

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： PRIYAL SHAH ,  RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  BRETT P. WILKERSON

    IPC: B23K20/02 ,  B23K20/24

    CPC classification number: B23K20/02 ,  B23K20/24 ,  B23K2101/40

    Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

    FANOUT MODULE INTEGRATING A PHOTONIC INTEGRATED CIRCUIT
    7.
    发明申请
    FANOUT MODULE INTEGRATING A PHOTONIC INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220342165A1

    公开(公告)日：2022-10-27

    申请号：US17361033

    申请日：2021-06-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： BRETT P. WILKERSON ,  RAJA SWAMINATHAN ,  KONG TOON NG ,  RAHUL AGARWAL

    IPC: G02B6/42

    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES
    8.
    发明申请
    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES 有权

    公开(公告)号：US20220319871A1

    公开(公告)日：2022-10-06

    申请号：US17843938

    申请日：2022-06-17

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  BRETT P. WILKERSON ,  LEI FU ,  RAHUL AGARWAL

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

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