公开(公告)号：US20240047229A1

公开(公告)日：2024-02-08

申请号：US17879110

申请日：2022-08-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： SRI RANGA SAI BOYAPATI ,  RAJA SWAMINATHAN ,  DEEPAK VASANT KULKARNI

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L21/486 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/6835

摘要： A method for forming a core for a substrate that removes portions of a resist layer based on a pattern specifying widths of removed portions of the resist layer. The method forms a set of pillars by plating the remaining portions of the resist layer with a conductive material, so each pillar of the set has a perimeter plated with the conductive material. Additionally, each pillar of the set of pillars is encapsulated with a dielectric material. In some implementations, the dielectric material is an organic material.

公开(公告)号：US20230069294A1

公开(公告)日：2023-03-02

申请号：US17563921

申请日：2021-12-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  JOHN WUU ,  MIHIR PANDYA ,  SAMUEL D. NAFFZIGER

IPC分类号： H01L23/538 ,  H01L23/48 ,  H01L25/18 ,  H01L25/00

摘要： A chip for multi-die communications couplings using a single bridge die, includes: a plurality of dies each including one or more functional circuit blocks; and a first bridge die directly communicatively coupling two or more pairs of dies of the plurality of dies.

公开(公告)号：US20240113004A1

公开(公告)日：2024-04-04

申请号：US17957444

申请日：2022-09-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： GABRIEL H. LOH ,  ERIC J. CHAPMAN ,  RAJA SWAMINATHAN

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9211

摘要： A semiconductor package assembly includes a package interface. An interposer die has a first surface and a second surface opposite to the first surface, where the first surface of the interposer is die positioned on the package interface. The interposer die includes a plurality of conductive connections between the first surface and second surface. A chiplet includes a connectivity region having conductive pathways, with a first portion of the connectivity region coupled to a conductive connection of the interposer die and a second portion of the connectivity region cantilevered from the interposer die.

公开(公告)号：US20240071940A1

公开(公告)日：2024-02-29

申请号：US18505187

申请日：2023-11-09

申请人： ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

发明人： RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  MICHAEL S. ALFANO ,  GABRIEL H. LOH ,  ALAN D. SMITH ,  GABRIEL WONG ,  MICHAEL MANTOR

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L25/065 ,  H01L27/06

CPC分类号： H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

摘要： A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

公开(公告)号：US20220199429A1

公开(公告)日：2022-06-23

申请号：US17554498

申请日：2021-12-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： PRIYAL SHAH ,  RAJA SWAMINATHAN ,  BRETT P. WILKERSON

IPC分类号： H01L21/48 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  H01L23/42 ,  H01L21/56

摘要： Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.

公开(公告)号：US20230268319A1

公开(公告)日：2023-08-24

申请号：US18046519

申请日：2022-10-14

申请人： ADVANCED MICRO DEVICES, INC.

发明人： RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  JOHN WUU

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/16 ,  H01L24/08 ,  H01L23/5226 ,  H01L21/76898 ,  H01L24/80 ,  H01L21/561 ,  H01L21/568 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06568

摘要： A semiconductor assembly includes a first die having a front side metallization layer. The semiconductor assembly also includes a second side having a front side metallization layer that is bonded to the front side metallization layer of the first die.

公开(公告)号：US20230130354A1

公开(公告)日：2023-04-27

申请号：US17512109

申请日：2021-10-27

申请人： ADVANCED MICRO DEVICES, INC.

发明人： RAHUL AGARWAL ,  RAJA SWAMINATHAN

IPC分类号： H01L25/16 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

摘要： A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.

公开(公告)号：US20220342165A1

公开(公告)日：2022-10-27

申请号：US17361033

申请日：2021-06-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： BRETT P. WILKERSON ,  RAJA SWAMINATHAN ,  KONG TOON NG ,  RAHUL AGARWAL

IPC分类号： G02B6/42

摘要： A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20220208712A1

公开(公告)日：2022-06-30

申请号：US17134601

申请日：2020-12-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： RAHUL AGARWAL ,  RAJA SWAMINATHAN

IPC分类号： H01L23/00 ,  H01L25/065

摘要： A method of manufacturing a semiconductor device, including: bonding a first chip layer comprising a first semiconductor chip to a second chip layer comprising a second semiconductor chip to electrically couple an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; and bonding a third chip layer comprising a third semiconductor chip to the second chip layer to electrically couple an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip.

公开(公告)号：US20240113070A1

公开(公告)日：2024-04-04

申请号：US17957483

申请日：2022-09-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： CHINTAN BUCH ,  RAJA SWAMINATHAN

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/94 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1432 ,  H01L2924/37001

摘要： A method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. A die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. One or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. A second wafer is coupled to a top surface of the die. An amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.