公开(公告)号：US20240143056A1

公开(公告)日：2024-05-02

申请号：US18218463

申请日：2023-07-05

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ILC

Inventor： Greg SADOWSKI ,  Sriram Sundarm ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

公开(公告)号：US20230205306A1

公开(公告)日：2023-06-29

申请号：US17561837

申请日：2021-12-24

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Joseph Lee Greathouse ,  Adam Neil Calder Clark ,  Stephen Kushnir

IPC: G06F1/3296

CPC classification number: G06F1/3296

Abstract: One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.

公开(公告)号：US20240192759A1

公开(公告)日：2024-06-13

申请号：US18065313

申请日：2022-12-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Stephen Kushnir ,  Sriram Sundaram ,  Christopher Allan Poirier

IPC: G06F1/3296 ,  G06F1/3228 ,  H01L25/065

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  H01L25/0652

Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

公开(公告)号：US11709536B2

公开(公告)日：2023-07-25

申请号：US17029852

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Greg Sadowski ,  Sriram Sundaram ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.