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    POWER MANAGEMENT OF CHIPLETS WITH VARYING PERFORMANCE
    1.
    发明公开
    POWER MANAGEMENT OF CHIPLETS WITH VARYING PERFORMANCE 审中-公开

    公开(公告)号：US20240192759A1

    公开(公告)日：2024-06-13

    申请号：US18065313

    申请日：2022-12-13

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Stephen Kushnir ,  Sriram Sundaram ,  Christopher Allan Poirier

    IPC: G06F1/3296 ,  G06F1/3228 ,  H01L25/065

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  H01L25/0652

    Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

    Multi-die system performance optimization
    2.
    发明授权
    Multi-die system performance optimization 有权

    公开(公告)号：US11709536B2

    公开(公告)日：2023-07-25

    申请号：US17029852

    申请日：2020-09-23

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Greg Sadowski ,  Sriram Sundaram ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

    IPC: G06F1/28 ,  G05F1/625

    CPC classification number: G06F1/28 ,  G05F1/625

    Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

    MISSION MODE VMIN PREDICTION AND CALIBRATION
    3.
    发明申请
    MISSION MODE VMIN PREDICTION AND CALIBRATION 有权

    公开(公告)号：US20220189576A1

    公开(公告)日：2022-06-16

    申请号：US17121110

    申请日：2020-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

    IPC: G11C29/50 ,  H03K3/03 ,  G11C7/22

    Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS
    4.
    发明公开
    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS 审中-公开

    公开(公告)号：US20230409392A1

    公开(公告)日：2023-12-21

    申请号：US17844558

    申请日：2022-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Christopher Allan Poirier ,  Samuel D. Naffziger

    IPC: G06F9/48 ,  G06F1/26

    CPC classification number: G06F9/4893 ,  G06F1/26

    Abstract: An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. A processing unit includes at least two replicated partitions, each assigned to operation parameters of a respective power domain. The partitions include multiple compute units. The compute units include multiple lanes of execution. Due to a variety of types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational compute units. To balance the throughput of the multiple partitions, a power manager generates both static and dynamic scaling factors based on at least the corresponding number of operational compute units. Using these scaling factors, the power manager adjusts the operation parameters of power domains for the partitions relative to one another.

    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS
    6.
    发明申请
    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS 有权

    公开(公告)号：US20220100249A1

    公开(公告)日：2022-03-31

    申请号：US17127681

    申请日：2020-12-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

    IPC: G06F1/28 ,  G06F1/30 ,  G01R31/40

    Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

    Mission mode Vmin prediction and calibration
    8.
    发明授权
    Mission mode Vmin prediction and calibration 有权

    公开(公告)号：US11462294B2

    公开(公告)日：2022-10-04

    申请号：US17121110

    申请日：2020-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

    IPC: G11C7/10 ,  G11C29/50 ,  G11C7/22 ,  H03K3/03

    Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

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