公开(公告)号：US12265441B2

公开(公告)日：2025-04-01

申请号：US17218795

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Dmitri Tikhostoup ,  Vladimir Giemborek ,  William Herz

IPC: G06F1/3287 ,  G06F1/26 ,  G06F1/3293 ,  G06T1/20

Abstract: Graphics processing unit (GPU) selection based on a utilized power source, including: determining that an apparatus is using a direct current (DC) power source instead of an Alternating Current (AC) power source; and causing, in response to the apparatus using the DC power source, the apparatus to preferentially utilize an integrated graphics processing unit (iGPU) over a discrete graphics processing unit (dGPU) while using the DC power source.

公开(公告)号：US12271627B2

公开(公告)日：2025-04-08

申请号：US17937292

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael John Austin ,  Dmitri Tikhostoup

IPC: G06F3/06

Abstract: An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node accesses a first memory and the second processing node accesses a second memory. A first communication channel transfers data between the first and second processing nodes. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.

公开(公告)号：US20240111452A1

公开(公告)日：2024-04-04

申请号：US17937292

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael John Austin ,  Dmitri Tikhostoup

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node uses a first memory and the second processing node uses a second memory. A first communication channel transfers data between the first processing node and the second processing node. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after determining a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.