公开(公告)号：US20140112066A1

公开(公告)日：2014-04-24

申请号：US14057222

申请日：2013-10-18

Applicant: Agency for Science, Technology and Research

Inventor： Kit Ho Melvin CHOW ,  Fei LI

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5607 ,  G11C13/0069

Abstract: In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated.

Abstract translation: 在各种实施例中，可以提供包括数据单元的电路装置。 电路装置还可以包括第一晶体管和第二晶体管。 第一晶体管的第一受控电极和第二晶体管的第一受控电极可以耦合到数据单元的第一电极。 第一晶体管的第二受控电极可以被配置为电连接到第一参考电压，使得当第一晶体管被激活时，数据单元的第一电极电连接到第一参考电压。 第二晶体管的第二受控电极可以被配置为电连接到第二参考电压，使得当第二晶体管被激活时，数据单元的第一电极电连接到第二参考电压。

公开(公告)号：US20140285226A1

公开(公告)日：2014-09-25

申请号：US14225367

申请日：2014-03-25

Applicant: Agency for Science, Technology and Research

Inventor： Fei LI ,  Kit Ho Melvin CHOW

IPC: G01R27/02

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0002 ,  G11C29/24 ,  G11C29/50008 ,  G11C2013/0054

Abstract: A method may include applying a first current through the memory element and a first selection component. The memory element and the first selection component may be located along a memory line. The method may also include measuring a first potential difference across the memory line. The method may further include applying a second current through a second selection component, wherein the second selection component is located along a dummy line, and measuring a second potential difference across the dummy line. The method may additionally include determining the resistance of the memory element based on the first potential difference and the second potential difference. The first selection component may be activated and the second selection component may be deactivated to apply the first current. The first selection component may be deactivated and the second selection component may be activated to apply the second current.

Abstract translation: 一种方法可以包括施加通过存储元件的第一电流和第一选择元件。 存储器元件和第一选择部件可以沿着存储器线定位。 该方法还可以包括测量跨越存储器线的第一电位差。 该方法可以进一步包括通过第二选择部件施加第二电流，其中第二选择部件沿虚拟线路定位，并测量穿过虚拟线路的第二电位差。 该方法可以另外包括基于第一电位差和第二电位差确定存储元件的电阻。 可以激活第一选择组件，并且可以停用第二选择组件以应用第一电流。 可以停用第一选择组件，并且可以激活第二选择组件以应用第二电流。

公开(公告)号：US20180005678A1

公开(公告)日：2018-01-04

申请号：US15543976

申请日：2015-12-31

Applicant: AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH

Inventor： Huey Chian FOONG ,  Fei LI

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/1673 ,  G11C5/025 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/222 ,  H01L27/228

Abstract: According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second array based on the first reference voltage.