公开(公告)号：US20180005678A1

公开(公告)日：2018-01-04

申请号：US15543976

申请日：2015-12-31

Applicant: AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH

Inventor： Huey Chian FOONG ,  Fei LI

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/1673 ,  G11C5/025 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/222 ,  H01L27/228

Abstract: According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second array based on the first reference voltage.

公开(公告)号：US20170243624A1

公开(公告)日：2017-08-24

申请号：US15517745

申请日：2015-10-15

Applicant: Agency For Science, Technology and Research

Inventor： Huey Chian FOONG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/412

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

公开(公告)号：US20140233331A1

公开(公告)日：2014-08-21

申请号：US14184645

申请日：2014-02-19

Applicant: Agency for Science, Technology and Research

Inventor： Huey Chian FOONG ,  Kejie HUANG

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/79

Abstract: According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished.

Abstract translation: 根据各种实施例，可以提供一种写入控制电路，其被配置为通过向存储器单元施加写入电流来控制对存储器单元的写入。 写控制电路可以包括：当前应用电路，被配置为将写入电流施加到存储单元; 确定电路，被配置为确定对所述存储单元的写入是否结束; 以及停止写入电路，其被配置为如果确定对存储器单元的写入结束，则从存储器单元切断写入电流。