公开(公告)号：US20170316976A1

公开(公告)日：2017-11-02

申请号：US15520821

申请日：2015-10-15

Applicant: ams AG

Inventor： Guenther KOPPITSCH ,  Bernhard LOEFFLER

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/3065

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L23/481

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

公开(公告)号：US20220059434A1

公开(公告)日：2022-02-24

申请号：US17415167

申请日：2019-12-20

Applicant: ams AG

Inventor： Bernhard LOEFFLER ,  Thomas BODNER ,  Joerg SIEGERT

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L21/768

Abstract: An intermetal dielectric and metal layers embedded in the intermetal dielectric are arranged on a substrate of semiconductor material. A via hole is formed in the substrate, and a metallization contacting a contact area of one of the metal layers is applied in the via hole. The metallization, the metal layer comprising the contact area and the intermetal dielectric are partially removed at the bottom of the via hole in order to form a hole penetrating the intermetal dielectric and extending the via hole. A continuous passivation is arranged on sidewalls within the via hole and the hole, and the metallization contacts the contact area around the hole. Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.

公开(公告)号：US20160322519A1

公开(公告)日：2016-11-03

申请号：US15107901

申请日：2014-12-12

Applicant: AMS AG

Inventor： Franz SCHRANK ,  Sara CARNIELLO ,  Hubert ENICHLMAIR ,  Jochen KRAFT ,  Bernhard LOEFFLER ,  Rainer HOLZHAIDER

IPC: H01L31/0224 ,  H01L31/103 ,  H01L31/18 ,  H01L31/0216

Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.

Abstract translation: 在半导体衬底（1）的主表面（10）上布置介电层（2），并且在介质层上布置钝化层（6）。 金属层（3）嵌入基板中的开口（12）上方的电介质层中，并且金属化层（14）布置在开口中。 金属化接触金属层，并通过基板的后表面（11）形成贯穿基板。 包含至少一个另外的层的层或层序列（7,8,9）布置在开口上方的钝化层上。 以这种方式，穿透基底通孔的底部是稳定的。 插头（17）还可以布置在开口中而不填充开口。