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公开(公告)号：US10224951B2
公开(公告)日：2019-03-05
申请号：US15276561
申请日：2016-09-26
Applicant: Analog Devices Global
Inventor： Venkata Aruna Srikanth Nittala , Avinash Gutta
Abstract: A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.
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公开(公告)号：US20170207907A1
公开(公告)日：2017-07-20
申请号：US15336414
申请日：2016-10-27
Applicant: Analog Devices Global
Inventor： Mayur Gurunath Anvekar , Venkata Aruna Srikanth Nittala , Roberto Sergio Matteo Maurino , Naiqian Ren
CPC classification number: H04L7/0331 , G01S7/521 , H04L7/0012 , H04L7/0029 , H04L41/0896
Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.
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公开(公告)号：US09294037B2
公开(公告)日：2016-03-22
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
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Patent Agency Ranking
公开(公告)号：US20180302101A1
公开(公告)日：2018-10-18
申请号：US15485919
申请日：2017-04-12
Applicant: Analog Devices Global
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala , Abhilasha Kawle
IPC: H03M3/00
Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
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公开(公告)号：US10103744B1
公开(公告)日：2018-10-16
申请号：US15485919
申请日：2017-04-12
Applicant: Analog Devices Global
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala , Abhilasha Kawle
Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
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公开(公告)号：US10461770B2
公开(公告)日：2019-10-29
申请号：US16015585
申请日：2018-06-22
Applicant: Analog Devices Global Unlimited Company
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala
Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.
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公开(公告)号：US09893877B2
公开(公告)日：2018-02-13
申请号：US15336414
申请日：2016-10-27
Applicant: Analog Devices Global
Inventor： Mayur Gurunath Anvekar , Venkata Aruna Srikanth Nittala , Roberto Sergio Matteo Maurino , Naiqian Ren
CPC classification number: H04L7/0331 , G01S7/521 , H04L7/0012 , H04L7/0029 , H04L41/0896
Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.
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公开(公告)号：US20150270805A1
公开(公告)日：2015-09-24
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
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