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Patent Agency Ranking
公开(公告)号：US10461770B2
公开(公告)日：2019-10-29
申请号：US16015585
申请日：2018-06-22
Applicant: Analog Devices Global Unlimited Company
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala
Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.
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公开(公告)号：US10224951B2
公开(公告)日：2019-03-05
申请号：US15276561
申请日：2016-09-26
Applicant: Analog Devices Global
Inventor： Venkata Aruna Srikanth Nittala , Avinash Gutta
Abstract: A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.
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公开(公告)号：US09455731B1
公开(公告)日：2016-09-27
申请号：US14819321
申请日：2015-08-05
Applicant: ANALOG DEVICES GLOBAL
Inventor： Avinash Gutta , Michael Coln
Abstract: A method and a digital-to-analog converter (DAC) circuit involve forming an analog signal using charge sharing operations. The DAC circuit includes a plurality of digital components with associated parasitic capacitances. The digital components are activated based on a digital input code, such that charge is shared among the parasitic capacitances to form a first analog signal proportional to the digital input code. The digital components can also be activated based on a complementary code to form a second analog signal. The first analog signal and the second analog signal can be used to form, as a final output of the DAC circuit, an analog signal that is linearly proportional to the digital input code.
Abstract translation: 一种方法和数模转换器（DAC）电路涉及使用电荷共享操作形成模拟信号。 DAC电路包括具有相关联的寄生电容的多个数字分量。 基于数字输入代码激活数字分量，使得在寄生电容之间共享电荷以形成与数字输入码成比例的第一模拟信号。 还可以基于互补码激活数字分量以形成第二模拟信号。 可以使用第一模拟信号和第二模拟信号来形成与数字输入码成线性比例的模拟信号，作为DAC电路的最终输出。
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公开(公告)号：US20180302101A1
公开(公告)日：2018-10-18
申请号：US15485919
申请日：2017-04-12
Applicant: Analog Devices Global
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala , Abhilasha Kawle
IPC: H03M3/00
Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
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公开(公告)号：US10103744B1
公开(公告)日：2018-10-16
申请号：US15485919
申请日：2017-04-12
Applicant: Analog Devices Global
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala , Abhilasha Kawle
Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
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