公开(公告)号：US09203426B2

公开(公告)日：2015-12-01

申请号：US14302173

申请日：2014-06-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Jialin Zhao ,  Richard E. Schreier ,  Jose Barreiro Silva ,  Hajime Shibata ,  Wenhua W. Yang ,  Yunzhi Dong

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/378 ,  H03M1/1019 ,  H03M1/1038 ,  H03M1/74 ,  H03M3/37 ,  H03M3/384 ,  H03M3/388 ,  H03M3/464

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不理想，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。