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公开(公告)号：US09178529B2
公开(公告)日：2015-11-03
申请号：US14057153
申请日：2013-10-18
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Hajime Shibata , Wenhua W. Yang , Richard E. Schreier
CPC classification number: H03M3/344 , H03M1/00 , H03M1/12 , H03M1/144 , H03M1/145 , H03M3/30 , H03M3/416 , H04L25/067 , H04M1/72519
Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.
Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。
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公开(公告)号：US20150123828A1
公开(公告)日：2015-05-07
申请号：US14073396
申请日：2013-11-06
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： David Nelson Alldred , Jipeng Li , Richard E. Schreier , Hajime Shibata
Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.
Abstract translation: 在一个示例实现中，本公开提供了一种在连续时间Σ-Δ模数转换器中使用的环路滤波器。 具体地，在一系列运算放大器积分器中的第一运算放大器的输入处提供电容反馈数模转换器路径。 在第一运算放大器的输入处的电容反馈数模转换器减少了第一运算放大器的输出处的信号内容，从而减小了第一运算放大器的输出摆幅。 输出摆幅的减小提供了更有效的环路滤波器。
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公开(公告)号：US09912144B2
公开(公告)日：2018-03-06
申请号：US14477236
申请日：2014-09-04
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Trevor Clifford Caldwell , Corey Petersen , David Nelson Alldred , Hajime Shibata
Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.
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Patent Agency Ranking
公开(公告)号：US09312840B2
公开(公告)日：2016-04-12
申请号：US14194107
申请日：2014-02-28
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
CPC classification number: H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。
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公开(公告)号：US20150249445A1
公开(公告)日：2015-09-03
申请号：US14194107
申请日：2014-02-28
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
CPC classification number: H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。
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公开(公告)号：US20150109158A1
公开(公告)日：2015-04-23
申请号：US14057153
申请日：2013-10-18
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Hajime Shibata , Wenhua W. Yang , Richard E. Schreier
IPC: H03M3/00
CPC classification number: H03M3/344 , H03M1/00 , H03M1/12 , H03M1/144 , H03M1/145 , H03M3/30 , H03M3/416 , H04L25/067 , H04M1/72519
Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.
Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。
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公开(公告)号：US09203426B2
公开(公告)日：2015-12-01
申请号：US14302173
申请日：2014-06-11
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Jialin Zhao , Richard E. Schreier , Jose Barreiro Silva , Hajime Shibata , Wenhua W. Yang , Yunzhi Dong
CPC classification number: H03M3/378 , H03M1/1019 , H03M1/1038 , H03M1/74 , H03M3/37 , H03M3/384 , H03M3/388 , H03M3/464
Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).
Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不理想，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。
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公开(公告)号：US09054731B2
公开(公告)日：2015-06-09
申请号：US14073396
申请日：2013-11-06
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： David Nelson Alldred , Jipeng Li , Richard E. Schreier , Hajime Shibata
Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.
Abstract translation: 在一个示例实现中，本公开提供了一种在连续时间Σ-Δ模数转换器中使用的环路滤波器。 具体地，在一系列运算放大器积分器中的第一运算放大器的输入处提供电容反馈数模转换器路径。 在第一运算放大器的输入处的电容反馈数模转换器减少了第一运算放大器的输出处的信号内容，从而减小了第一运算放大器的输出摆幅。 输出摆幅的减小提供了更有效的环路滤波器。
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