Abstract:
A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.
Abstract:
A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.