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    Performing Multiple Bit Computation and Convolution in Memory
    2.
    发明申请
    Performing Multiple Bit Computation and Convolution in Memory 有权

    公开(公告)号：US20220156045A1

    公开(公告)日：2022-05-19

    申请号：US16953093

    申请日：2020-11-19

    Applicant: Apple Inc.

    Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

    IPC: G06F7/544 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46

    Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.

    Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array
    3.
    发明授权
    Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array 有权
    用于抑制存储器阵列中相同存储器元件的同时读和写字线访问的装置

    公开(公告)号：US09001593B2

    公开(公告)日：2015-04-07

    申请号：US13725180

    申请日：2012-12-21

    Applicant: Apple Inc.

    Inventor： Hitesh Gupta ,  Greg M Hess ,  Aravind Kandala

    IPC: G11C16/10 ,  G11C8/08

    CPC classification number: G11C8/08 ,  G11C8/10

    Abstract: A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.

    Abstract translation: 存储器阵列包括多个字线，每个字线耦合到用于存储器写入操作的字线驱动器和用于存储器读取操作的字线驱动器。 解码级包括每个字线的写逻辑和每个字线的读逻辑。 字线驱动器级包括写字线驱动器和读字线驱动器。 用于至少一个世界线的写入逻辑被配置为使得写入字线驱动器能够进行字线的存储器写入操作，同时禁止读取字线逻辑使读取字线驱动器用于字线的存储器读取操作 。

    LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE
    4.
    发明申请
    LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE 有权
    低功耗双泵浦多端口注册文件架构

    公开(公告)号：US20160055889A1

    公开(公告)日：2016-02-25

    申请号：US14467376

    申请日：2014-08-25

    Applicant: Apple Inc.

    Inventor： Ajay Kumar Bhatia ,  Aravind Kandala

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/419 ,  G11C2207/2254 ,  G11C2207/229

    Abstract: Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.

    Abstract translation: 公开了可以允许选择性地调整存储器内的各个写入路径的延迟的实施例。 存储器可以包括存储器阵列，第一数据锁存器，第二数据锁存器和电路。 响应于检测到第一时钟信号的第一边缘，第一和第二数据锁存器可以被配置为对各自的数据值进行采样。 电路可以被配置为检测第一时钟信号的第一边缘，并且响应于检测到第一时钟信号的第一边缘而选择第一数据锁存器的输出。 电路可以检测第一时钟信号的后续相对边缘，并且响应于对第一时钟信号的相对边缘采样来选择第二数据锁存器的输出。

    Low power double pumped multi-port register file architecture
    6.
    发明授权
    Low power double pumped multi-port register file architecture 有权
    低功率双泵浦多端口寄存器文件架构

    公开(公告)号：US09361959B2

    公开(公告)日：2016-06-07

    申请号：US14467376

    申请日：2014-08-25

    Applicant: Apple Inc.

    Inventor： Ajay Kumar Bhatia ,  Aravind Kandala

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/419 ,  G11C2207/2254 ,  G11C2207/229

    Abstract: Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.

    Abstract translation: 公开了可以允许选择性地调整存储器内的各个写入路径的延迟的实施例。 存储器可以包括存储器阵列，第一数据锁存器，第二数据锁存器和电路。 响应于检测到第一时钟信号的第一边缘，第一和第二数据锁存器可以被配置为对各自的数据值进行采样。 电路可以被配置为检测第一时钟信号的第一边缘，并且响应于检测到第一时钟信号的第一边缘而选择第一数据锁存器的输出。 电路可以检测第一时钟信号的后续相对边缘，并且响应于对第一时钟信号的相对边缘采样来选择第二数据锁存器的输出。

    APPARATUS TO SUPPRESS CONCURRENT READ AND WRITE WORD LINE ACCESS OF THE SAME MEMORY ELEMENT IN A MEMORY ARRAY
    7.
    发明申请
    APPARATUS TO SUPPRESS CONCURRENT READ AND WRITE WORD LINE ACCESS OF THE SAME MEMORY ELEMENT IN A MEMORY ARRAY 有权
    用于在存储器阵列中抑制同时读取和写入字线访问相同存储元件的装置

    公开(公告)号：US20140177346A1

    公开(公告)日：2014-06-26

    申请号：US13725180

    申请日：2012-12-21

    Applicant: APPLE INC.

    Inventor： Hitesh Gupta ,  Greg M. Hess ,  Aravind Kandala

    IPC: G11C8/08

    CPC classification number: G11C8/08 ,  G11C8/10

    Abstract: A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.

    Abstract translation: 存储器阵列包括多个字线，每个字线耦合到用于存储器写入操作的字线驱动器和用于存储器读取操作的字线驱动器。 解码级包括每个字线的写逻辑和每个字线的读逻辑。 字线驱动器级包括写字线驱动器和读字线驱动器。 用于至少一个世界线的写入逻辑被配置为使得写入字线驱动器能够进行字线的存储器写入操作，同时禁止读取字线逻辑使读取字线驱动器用于字线的存储器读取操作 。

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