公开(公告)号：US09747239B2

公开(公告)日：2017-08-29

申请号：US14467164

申请日：2014-08-25

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Munetoshi Fukami ,  Manu Gulati

IPC: G06F1/00 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4022 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.

公开(公告)号：US20160026234A1

公开(公告)日：2016-01-28

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US20150026041A1

公开(公告)日：2015-01-22

申请号：US13944462

申请日：2013-07-17

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Munetoshi Fukami ,  Kevin C. Wong

IPC: G06Q20/38 ,  G06Q20/24

CPC classification number: G06Q20/38 ,  G06F17/5045 ,  G06F17/505 ,  G06Q20/24

Abstract: Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.

Abstract translation: 公开了本地接口单元的实施例，其可以允许作为流控制方法的一部分来管理信用和令牌。 本地接口单元可以包括发送单元和接收单元。 发送单元可以被配置为接收信用和令牌，基于所接收的令牌的数量来确定可用的信用数量，基于接收到的令牌的数量确定令牌的可用数量，并将可用信用发送到仲裁单元。 然后可以通过发送单元响应于从仲裁接收到所选择的交易而更新可用信用，并且发送单元然后可以发送所选择的交易，并且一旦交易被发送，就更新可用信用和可用令牌。 接收单元可以被配置为向发送单元发送信用和令牌，并且接收由发送单元发送的交易。

公开(公告)号：US09310783B2

公开(公告)日：2016-04-12

申请号：US13719517

申请日：2012-12-19

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Gurjeet S Saund ,  Munetoshi Fukami ,  Shane J Keil

IPC: G05B11/01 ,  G06F1/32

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。 功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

公开(公告)号：US20160055110A1

公开(公告)日：2016-02-25

申请号：US14467164

申请日：2014-08-25

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Munetoshi Fukami ,  Manu Gulati

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4022 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.

Abstract translation: 公开了用于片上通信网络的事务过滤器。 在一个实施例中，集成电路（IC）包括多个功能电路块，其中一些可以被置于休眠模式（例如，电源门控）。 IC还包括多个事务过滤器，每个事务过滤器都与唯一的一个功能电路块相关联。 响应于其相关联的功能电路块生成事务，给定的事务过滤器可以确定事务处理的功能电路块是否处于睡眠模式。 如果确定事务发往当前处于睡眠模式的功能电路块，则事务过滤器可以阻止该事务被传送。

公开(公告)号：US09270610B2

公开(公告)日：2016-02-23

申请号：US13778482

申请日：2013-02-27

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S Saund ,  Kevin C Wong ,  Munetoshi Fukami

IPC: H04L12/865 ,  H04L12/863 ,  H04W28/10

CPC classification number: H04L47/6275 ,  H04L47/6205 ,  H04L47/6295 ,  H04W28/10

Abstract: Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an IC includes a communications fabric connecting multiple agents to one another. Each agent may include an interface coupling itself to at least one other agent. Each interface may include multiple queues for storing information corresponding to pending transactions. Also included in each interface is an arbitration unit and control logic. The control logic may determine which transactions are presented to the arbitration unit for arbitration. In one embodiment, the control logic may inhibit certain transactions from being presented to the arbitration unit so that other higher priority transactions may advance. In another embodiment, the control logic may reduce the priority level of some transactions for arbitration purposes to prevent the blocking of other higher priority transactions.

Abstract translation: 公开了用于控制通信结构中的事务流的方法和装置的各种实施例。 在一个实施例中，IC包括将多个代理彼此连接的通信结构。 每个代理可以包括将自身耦合到至少一个其他代理的接口。 每个接口可以包括用于存储对应于待处理事务的信息的多个队列。 每个接口中还包括一个仲裁单元和控制逻辑。 控制逻辑可以确定哪些事务被呈现给仲裁单元进行仲裁。 在一个实施例中，控制逻辑可以禁止某些交易被呈现给仲裁单元，使得其他更高优先级的事务可以提前。 在另一个实施例中，控制逻辑可以减少用于仲裁目的的一些交易的优先级，以防止阻塞其他更高优先级的事务。

公开(公告)号：US10802968B2

公开(公告)日：2020-10-13

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/0815 ,  G06F12/0813 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

公开(公告)号：US09280503B2

公开(公告)日：2016-03-08

申请号：US13861696

申请日：2013-04-12

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Munetoshi Fukami

IPC: G06F13/37 ,  G06F13/36

CPC classification number: G06F13/37 ,  G06F13/36

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract translation: 在一个实施例中，仲裁器可以实现具有延迟加权重载机制的赤字加权循环方案。 所述延迟可以大于或等于所述织物时钟与不具有交易但具有未消耗权重（或交易速率的差别的另一措施）的一个或多个源相关联的较慢时钟的比率。 如果在延迟期间从一个或多个源提供事务，则可以防止权重的重新加载。 在一些实施例中，仲裁器可以被扩充以改善在一些接口上的带宽的使用，其中一些事务可能被限制一段时间。 仲裁器可以实现执行循环仲裁的第一个指针。 如果第一指针指示其事务被临时阻止的源，则第二指针可以从主指针的当前位置向前搜索以定位未阻塞的事务。

公开(公告)号：US09082118B2

公开(公告)日：2015-07-14

申请号：US13944462

申请日：2013-07-17

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Munetoshi Fukami ,  Kevin C. Wong

IPC: G06F17/50 ,  G06Q20/38 ,  G06Q20/24

CPC classification number: G06Q20/38 ,  G06F17/5045 ,  G06F17/505 ,  G06Q20/24

Abstract: Embodiments of a local interface unit are disclosed that may allow for managing credits and tokens as part of flow control method. The local interface unit may include a transmit unit and a receive unit. The transmit unit may be configured to receive credits and tokens, determine an available number of credits based on the number received tokens, determine an available number of tokens based on the number of received tokens, and send the available credits to an arbitration unit. The available credits may then be updated, by the transmit unit in response to receiving a selected transaction from the arbitration, and the transmit unit may then transmit the selected transaction, and update the available credits and the available tokens once the transaction has been sent. The receive unit may be configured to send credits and tokens to a transmit unit, and receive a transaction sent by a transmit unit.

Abstract translation: 公开了本地接口单元的实施例，其可以允许作为流控制方法的一部分来管理信用和令牌。 本地接口单元可以包括发送单元和接收单元。 发送单元可以被配置为接收信用和令牌，基于所接收的令牌的数量来确定可用的信用数量，基于接收到的令牌的数量确定令牌的可用数量，并将可用信用发送到仲裁单元。 然后可以通过发送单元响应于从仲裁接收到所选择的交易而更新可用信用，并且发送单元然后可以发送所选择的交易，并且一旦交易被发送，就更新可用信用和可用令牌。 接收单元可以被配置为向发送单元发送信用和令牌，并且接收由发送单元发送的交易。

公开(公告)号：US09860841B2

公开(公告)日：2018-01-02

申请号：US14831438

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Munetoshi Fukami ,  Srinivasa R. Sridharan ,  Harshavardhan Kaushikkar

IPC: H04W52/02 ,  H04L12/773 ,  H04L12/855

CPC classification number: H04W52/0251 ,  H04L45/60 ,  H04L47/2466 ,  Y02D70/00 ,  Y02D70/26

Abstract: Techniques are disclosed relating to a split communications fabric topology. In some embodiments, an apparatus includes a communications fabric structure with multiple fabric units. The fabric units may be configured to arbitrate among control packets of different messages. In some embodiments, a processing element is configured to generate a message that includes a control packet and one or more data packets. In some embodiments, the processing element is configured to transmit the control packet to a destination processing element (e.g., a memory controller) via the communications fabric structure and transmit the data packets to a data buffer. In some embodiments, the destination processing element is configured to retrieve the data packets from the data buffer in response to receiving the control packet via the hierarchical fabric structure. In these embodiments, bypassing the fabric structure for data packets may reduce power consumption.