公开(公告)号：US09325287B2

公开(公告)日：2016-04-26

申请号：US14162896

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

IPC: H03F3/45 ,  H03G3/30

CPC classification number: H03G3/30 ,  H03G1/0029

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出。

公开(公告)号：US10014876B1

公开(公告)日：2018-07-03

申请号：US15451194

申请日：2017-03-06

Applicant: Applied Micro Circuits Corporation

Inventor： Nanda Govind Jayaraman

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/38

CPC classification number: H03M1/38 ,  H03M1/1215 ,  H03M1/1245

Abstract: System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.

公开(公告)号：US09496884B1

公开(公告)日：2016-11-15

申请号：US15076338

申请日：2016-03-21

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Nanda Govind Jayaraman

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/1023 ,  H03M1/00 ,  H03M1/12 ,  H03M1/361

Abstract: System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

Abstract translation: 基于ADC的数字输出，在背景中校准ADC中替代比较器的直流偏移的系统和方法。 与多个样本的A / D转换并行，校准逻辑使用两个计数器来分别表示落入第一模拟范围和第二模拟范围的采样的ADC输出的出现。 两个范围对称关于MSB参考电压，并且组合覆盖该位的标称电压范围。 基于两个计数之间的差和两个计数的和的比率导出DC偏移。 校准逻辑可以可选地校准比较器。 可以基于与其相关联的各种位置来连续校准每个比较器。

公开(公告)号：US20150326197A1

公开(公告)日：2015-11-12

申请号：US14162896

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

IPC: H03G3/30

CPC classification number: H03G3/30 ,  H03G1/0029

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port

Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出