公开(公告)号：US09787519B2

公开(公告)日：2017-10-10

申请号：US14466327

申请日：2014-08-22

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Dariush Dabiri ,  Tarun Gupta ,  Venkatesh Nagapudi

IPC: H03M13/25 ,  H04L27/34 ,  H04L5/14 ,  H04B1/38 ,  H04B3/02 ,  H04L27/00 ,  H04L1/00 ,  H03M13/39 ,  H04L7/04 ,  H03M13/13

CPC classification number: H03M13/29 ,  H03M13/1102 ,  H03M13/134 ,  H03M13/152 ,  H03M13/19 ,  H03M13/253 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3916 ,  H03M13/616 ,  H03M13/63 ,  H04B1/38 ,  H04B3/02 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0061 ,  H04L1/0067 ,  H04L5/14 ,  H04L5/1423 ,  H04L7/042 ,  H04L27/0002 ,  H04L27/3483

Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

公开(公告)号：US09736000B2

公开(公告)日：2017-08-15

申请号：US14179727

申请日：2014-02-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Dariush Dabiri ,  Tarun Gupta ,  Venkatesh Nagapudi

IPC: H03M13/25 ,  H04L27/34 ,  H04L5/14 ,  H04B1/38 ,  H04B3/02 ,  H04L27/00 ,  H04L1/00 ,  H03M13/39 ,  H04L7/04 ,  H03M13/13

CPC classification number: H03M13/29 ,  H03M13/1102 ,  H03M13/134 ,  H03M13/152 ,  H03M13/19 ,  H03M13/253 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3916 ,  H03M13/616 ,  H03M13/63 ,  H04B1/38 ,  H04B3/02 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0061 ,  H04L1/0067 ,  H04L5/14 ,  H04L5/1423 ,  H04L7/042 ,  H04L27/0002 ,  H04L27/3483

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

公开(公告)号：US20170097838A1

公开(公告)日：2017-04-06

申请号：US13838624

申请日：2013-03-15

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Venkatesh Nagapudi ,  Satsheel B. Altekar

IPC: G06F9/455 ,  G06F9/22 ,  H04L29/08

CPC classification number: G06F9/45558 ,  G06F9/223 ,  G06F2009/45579 ,  G06F2009/45595 ,  H04L45/00 ,  H04L63/20 ,  H04L67/02 ,  H04L67/1002

Abstract: Various embodiments provide for a system that integrates 64 bit ARM cores and a switch on a single chip. The RISC style processors use highly optimized sets of instructions rather than the specialized set of instructions found in other architectures (e.g., x86). The system also includes multiple high bandwidth ports that enable multi-ported virtual appliances to be built using a single chip. The virtual appliances are software implemented versions of the physical appliances that are installed with servers to provide network services such routing and switching services, firewall, VPN, SSL, and other security services, as well as load balancing. The virtual appliances are implemented in software and the system can add new virtual appliances, or change the functions performed by existing virtual appliances flexibly without having to install or remove physical hardware.

公开(公告)号：US20150326379A1

公开(公告)日：2015-11-12

申请号：US14179727

申请日：2014-02-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Dariush Dabiri ,  Tarun Gupta ,  Venkatesh Nagapudi

IPC: H04L5/14

CPC classification number: H03M13/29 ,  H03M13/1102 ,  H03M13/134 ,  H03M13/152 ,  H03M13/19 ,  H03M13/253 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3916 ,  H03M13/616 ,  H03M13/63 ,  H04B1/38 ,  H04B3/02 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0061 ,  H04L1/0067 ,  H04L5/14 ,  H04L5/1423 ,  H04L7/042 ,  H04L27/0002 ,  H04L27/3483

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

Abstract translation: 有线系统和组件集成了减少数量的双轴铜对，以传输速度大于或等于每千兆字节的传输速度传输和接收全双工传输信号。 双轴向铜对的数量减少包括四个或更少的双轴铜对，其中每对形成单个双轴全双工电缆，用于信号的无源或主动通信。 处理器可以与双轴铜对集成，以对信号进行编码以实现快速传输速度。

公开(公告)号：US20150326376A1

公开(公告)日：2015-11-12

申请号：US14466327

申请日：2014-08-22

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Dariush Dabiri ,  Tarun Gupta ,  Venkatesh Nagapudi

IPC: H04L5/14 ,  H04B3/02 ,  H04B1/38

CPC classification number: H03M13/29 ,  H03M13/1102 ,  H03M13/134 ,  H03M13/152 ,  H03M13/19 ,  H03M13/253 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3916 ,  H03M13/616 ,  H03M13/63 ,  H04B1/38 ,  H04B3/02 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0061 ,  H04L1/0067 ,  H04L5/14 ,  H04L5/1423 ,  H04L7/042 ,  H04L27/0002 ,  H04L27/3483

Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

Abstract translation: 电缆系统和组件集成了减少数量的双轴电缆，以传输速度大于或等于每千兆字节的传输速度传输和接收全双工传输信号。 双轴向电缆的数量减少包括四个或更少的双轴向电缆，其中每对形成单个双轴全双工电缆，用于同时以多个不同传输速率无源或主动地通信信号。 处理器可以与双轴向电缆集成，并且以不同的传输速率对信号进行编码以实现快速传输速度。