公开(公告)号：US20180107606A1

公开(公告)日：2018-04-19

申请号：US15294031

申请日：2016-10-14

Applicant: ARM LIMITED

Inventor： Barry Duane WILLIAMSON ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Adrian MONTERO ,  Miles Robert DOOLEY

IPC: G06F12/1045 ,  G06F12/128 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/69

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

公开(公告)号：US20180107604A1

公开(公告)日：2018-04-19

申请号：US15293467

申请日：2016-10-14

Applicant: ARM LIMITED

Inventor： Miles Robert DOOLEY ,  ABHISHEK RAJA ,  Barry Duane WILLIAMSON ,  Huzefa Moiz SANJELIWALA

IPC: G06F12/1009 ,  G06F12/0802

CPC classification number: G06F12/1009 ,  G06F12/0802 ,  G06F12/1027 ,  G06F2212/60 ,  G06F2212/651 ,  G06F2212/681 ,  G06F2212/682

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address. The control circuitry is arranged, when performing the allocation process, to apply an allocation policy that permits each of the entries to be used for any of the different types of address translation data, and to store type identification data in association with each entry to enable the type of the address translation data stored therein to be determined. Such an approach enables very efficient usage of the address translation cache resources, for example by allowing the proportion of the entries used for full address translation data and the proportion of the entries used for partial address translation data to be dynamically adapted to changing workload conditions.