公开(公告)号：US09450571B2

公开(公告)日：2016-09-20

申请号：US14294593

申请日：2014-06-03

Applicant: ARM LIMITED

Inventor： Marlin Wayne Frederick, Jr. ,  Ashwani Kumar Srivastava

IPC: H03K5/02

CPC classification number: H03K5/02

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

Abstract translation: 集成电路2具有处理沿着数据通路14通过的数据信号的数据处理电路。耦合到数据处理电路的时钟电路用于调节数据信号沿数据路径的通过。 数据信号以数据信号电压幅度提供，并且以不同的时钟信号电压幅度提供时钟信号。 时钟信号电压幅度高于数据信号电压幅度。 除了数据电源网格10之外还提供了单独的时钟信号电源网格12。

公开(公告)号：US20230095459A1

公开(公告)日：2023-03-30

申请号：US17487477

申请日：2021-09-28

Applicant: Arm Limited

Inventor： Rakshith C ,  Denil Das Kolady ,  Ashwani Kumar Srivastava

IPC: H01L27/092 ,  H01L21/8238

Abstract: Various implementations described herein refer to a device having a cell structure with multiple transistors including active n-type transistors and active p-type transistors disposed together within a cell boundary. The active n-type transistors may have a first diffusion region formed within the cell boundary at a first end of the cell structure. The active p-type transistors may have a second diffusion region formed within the cell boundary at a second end of the cell structure. The active p-type transistors may have a vacated region cut-out from the second diffusion region, and/or the active n-type transistors may have a vacated region cut-out from the first diffusion region.

公开(公告)号：US20240329153A1

公开(公告)日：2024-10-03

申请号：US18127871

申请日：2023-03-29

Applicant: Arm Limited

Inventor： Ashwani Kumar Srivastava ,  Yves Thomas Laplanche ,  Ramesh Manohar

IPC: G01R31/52

CPC classification number: G01R31/52

Abstract: Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.

公开(公告)号：US09647660B1

公开(公告)日：2017-05-09

申请号：US15230247

申请日：2016-08-05

Applicant: ARM Limited

Inventor： Akhtar Waseem Alam ,  Ashwani Kumar Srivastava ,  Kunal Girish Bannore

IPC: H03L5/00 ,  H03K19/003 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K19/00361 ,  H03K3/356113 ,  H03K19/018521

Abstract: Apparatus for converting a first input signal from a first voltage domain to an output signal for a second voltage domain, the apparatus configured to operate within the first voltage domain or within the second voltage domain. The apparatus comprising input driver circuitry configured to generate second input signal based on the first input signal and a control signal received by input driver circuitry. The apparatus also comprising selection circuitry configured to generate a selection signal based on the control signal. The apparatus also comprising cross-coupled circuitry configured to generate a level-shifted signal at an intermediate node based on the first input signal, the second input signal, and the selection signal. The cross-coupled circuitry comprises a first pair of parallel transistors and a second pair of parallel transistors. The apparatus further comprising output driver circuitry configured to generate output signal for the second voltage domain based on the level-shifted signal.

公开(公告)号：US20150349760A1

公开(公告)日：2015-12-03

申请号：US14294593

申请日：2014-06-03

Applicant: ARM LIMITED

Inventor： Marlin Wayne FREDERICK, JR. ,  Ashwani Kumar Srivastava

IPC: H03K5/02

CPC classification number: H03K5/02

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

Abstract translation: 集成电路2具有处理沿着数据通路14通过的数据信号的数据处理电路。耦合到数据处理电路的时钟电路用于调节数据信号沿数据路径的通过。 数据信号以数据信号电压幅度提供，并且以不同的时钟信号电压幅度提供时钟信号。 时钟信号电压幅度高于数据信号电压幅度。 除了数据电源网格10之外还提供了单独的时钟信号电源网格12。