公开(公告)号：US10269783B2

公开(公告)日：2019-04-23

申请号：US15004852

申请日：2016-01-22

Applicant: ARM Limited

Inventor： Abhilash V. Thazhathidathil ,  Denil Das Kolady ,  Anand Dhanalakshmi Ramdass

IPC: H01L21/74 ,  H01L27/02 ,  H01L29/06 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a cell having a first region designated for a first type of implant and a second region designated for a second type of implant that is different than the first type of implant. The integrated circuit may include a first implant structure configured to implant the first region with the first type of implant such that the first region extends within a portion of the second region. The integrated circuit may include a second implant structure configured to implant the second region with the second type of implant such that the second region extends within a portion of the first region.

公开(公告)号：US11449116B2

公开(公告)日：2022-09-20

申请号：US16584904

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Soutani Bala Venkatanaga Durga Prasad ,  Denil Das Kolady ,  Anand Dhanalakshmi Ramdass

IPC: G06F30/394 ,  G06F1/28

Abstract: Various implementations described herein refer to a method for providing a cell layout with a power grid distribution network. The method may include analyzing porosity of the cell layout to identify blocked tracks and unblocked tracks. The method may include marking the unblocked tracks as available sites for stitching power rails of the cell layout to the power grid distribution network. The method may include generating a porosity report for the cell layout, and the porosity report may list the available sites as modifiable to enhance power grid porosity of the cell layout.

公开(公告)号：US20170213814A1

公开(公告)日：2017-07-27

申请号：US15004852

申请日：2016-01-22

Applicant: ARM Limited

Inventor： Abhilash V. Thazhathidathil ,  Denil Das Kolady ,  Anand Dhanalakshmi Ramdass

IPC: H01L27/02 ,  H01L23/522 ,  H01L21/265 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/26513 ,  H01L21/743 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11807 ,  H01L29/0688 ,  H01L2027/11861

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a cell having a first region designated for a first type of implant and a second region designated for a second type of implant that is different than the first type of implant. The integrated circuit may include a first implant structure configured to implant the first region with the first type of implant such that the first region extends within a portion of the second region. The integrated circuit may include a second implant structure configured to implant the second region with the second type of implant such that the second region extends within a portion of the first region.

公开(公告)号：US20240249790A1

公开(公告)日：2024-07-25

申请号：US18100614

申请日：2023-01-24

Applicant: Arm Limited

Inventor： Yannis Jallamion-Grive ,  Yunpeng Cai ,  Mohammed Adnan Addou ,  Anil Kumar Baratam ,  Denil Das Kolady ,  Chandru Tavarekere Krishnegowda ,  Jad Mohdad ,  Yves Thomas Laplanche ,  Yannick Marc Nevers

IPC: G11C29/30 ,  G11C29/12

CPC classification number: G11C29/30 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/3202

Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.

公开(公告)号：US20230095459A1

公开(公告)日：2023-03-30

申请号：US17487477

申请日：2021-09-28

Applicant: Arm Limited

Inventor： Rakshith C ,  Denil Das Kolady ,  Ashwani Kumar Srivastava

IPC: H01L27/092 ,  H01L21/8238

Abstract: Various implementations described herein refer to a device having a cell structure with multiple transistors including active n-type transistors and active p-type transistors disposed together within a cell boundary. The active n-type transistors may have a first diffusion region formed within the cell boundary at a first end of the cell structure. The active p-type transistors may have a second diffusion region formed within the cell boundary at a second end of the cell structure. The active p-type transistors may have a vacated region cut-out from the second diffusion region, and/or the active n-type transistors may have a vacated region cut-out from the first diffusion region.

公开(公告)号：US20210096627A1

公开(公告)日：2021-04-01

申请号：US16584904

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Soutani Bala Venkatanaga Durga Prasad ,  Denil Das Kolady ,  Anand Dhanalakshmi Ramdass

IPC: G06F1/28 ,  G06F17/50

Abstract: Various implementations described herein refer to a method for providing a cell layout with a power grid distribution network. The method may include analyzing porosity of the cell layout to identify blocked tracks and unblocked tracks. The method may include marking the unblocked tracks as available sites for stitching power rails of the cell layout to the power grid distribution network. The method may include generating a porosity report for the cell layout, and the porosity report may list the available sites as modifiable to enhance power grid porosity of the cell layout.