公开(公告)号：US20160180896A1

公开(公告)日：2016-06-23

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus YEUNG ,  Fakhruddin Ali BOHRA ,  Mudit BHARGAVA ,  Andy Wangkun CHEN ,  Yew Keong CHONG

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract translation: 存储器2包括存储元件4的规则阵列。写入多路复用器8的规则阵列被提供在存储元件4的规则阵列之外。存储元件间距与写多路复用器间距匹配。 写多路复用器10支持多个写端口。 当形成存储器设计2时，可以根据要支持的写入端口的期望数量来选择写入多路复用器8的阵列的给定实例，并且与常规形式的存储元件阵列4组合。

公开(公告)号：US20150091609A1

公开(公告)日：2015-04-02

申请号：US14088570

申请日：2013-11-25

Applicant: ARM LIMITED

Inventor： Srinivasan SRINATH ,  Ambica ASHOK ,  Fakhruddin Ali BOHRA

IPC: H03K19/017 ,  H03K19/094 ,  H03K19/00

CPC classification number: H03K19/01721 ,  G11C7/12 ,  G11C11/419 ,  H03K19/0013 ,  H03K19/09429 ,  H03K19/0963

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract translation: 集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。 信号辅助电路包括第一和第二辅助电路。 第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑 下拉转换后的低信号电平。 通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。