公开(公告)号：US20150085586A1

公开(公告)日：2015-03-26

申请号：US14037413

申请日：2013-09-26

Applicant: ARM LIMITED

Inventor： Bo ZHENG ,  Jungtae KWON ,  Gus YEUNG ,  Yew Keong CHONG

IPC: G11C7/12 ,  G06F17/50

CPC classification number: G11C7/12 ,  G11C7/1096

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号识别哪个列包含寻址的存储器单元。

公开(公告)号：US20140250278A1

公开(公告)日：2014-09-04

申请号：US13782077

申请日：2013-03-01

Applicant: ARM LIMITED

Inventor： Gus YEUNG ,  Bo ZHENG ,  Frank GUO

IPC: G11C7/00 ,  G06F12/00

CPC classification number: G06F12/00 ,  G11C5/147 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/417

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Abstract translation: 集成电平移位锁存电路接收第一电压域中的输入信号并在第二电压域中产生输出信号。 数据保持电路在透明阶段工作，其中数据值经受电平移位功能，并根据输入信号写入数据保持电路。 控制电路控制数据保持电路在时钟信号的第一阶段期间在透明阶段中工作，并且在时钟信号的第二阶段期间操作在锁存阶段。 写入电路将数据值写入数据保持电路。 竞争缓解电路在透明阶段期间减少数据保持电路内的至少一个组件的压降。

公开(公告)号：US20160180896A1

公开(公告)日：2016-06-23

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus YEUNG ,  Fakhruddin Ali BOHRA ,  Mudit BHARGAVA ,  Andy Wangkun CHEN ,  Yew Keong CHONG

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract translation: 存储器2包括存储元件4的规则阵列。写入多路复用器8的规则阵列被提供在存储元件4的规则阵列之外。存储元件间距与写多路复用器间距匹配。 写多路复用器10支持多个写端口。 当形成存储器设计2时，可以根据要支持的写入端口的期望数量来选择写入多路复用器8的阵列的给定实例，并且与常规形式的存储元件阵列4组合。

公开(公告)号：US20150009772A1

公开(公告)日：2015-01-08

申请号：US13936512

申请日：2013-07-08

Applicant: ARM Limited

Inventor： Wang-Kun CHEN ,  Yew Keong CHONG ,  Sriram THYAGARAJAN ,  Gus YEUNG

IPC: G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148

Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Abstract translation: 存储器具有正常模式和省电模式。 存储器具有位线预充电电路，其在正常模式期间选择性地将一对位线耦合到预充电节点，以将位线充电到给定的电压电平。 在省电模式期间，位线与预充电节点隔离。 提供电压控制电路以在正常模式期间将预充电节点保持在第一电压电平，并且在省电模式期间处于小于第一电压电平的第二电压电平。 通过在省电模式下减小预充电节点处的电压电平，可以减少从省电模式切换到正常模式时所产生的浪涌电流量，并且能够在从省电模式返回时减少唤醒时间 正常模式。

公开(公告)号：US20140247081A1

公开(公告)日：2014-09-04

申请号：US13782120

申请日：2013-03-01

Applicant: ARM LIMITED

Inventor： Gus YEUNG ,  Srinivasan SRINATH ,  Fakhruddin ALI BOHRA

IPC: H03K19/0185

CPC classification number: H03K19/0185

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching.

Abstract translation: 集成电平移位组合电路在第一电压域中接收多个输入信号，并执行组合操作以在第二电压域中产生输出信号。 电路包括组合电路，其包括在相应的第一和第二电压域中操作的第一组合电路部分和第二组合电路部分。 第二组合电路部分具有输出节点，其电压电平标识输出信号的值，并且包括对由第一组合电路部分产生的中间信号施加电平移位功能的反馈电路。 在组合电路的组合操作的性能导致组合电路切换输出节点上的电压的情况下，争用减轻电路减少了反馈电路内的至少一个组件上的电压降，争用缓解电路因此有助于组合电路 在输出节点电压切换。

公开(公告)号：US20140115554A1

公开(公告)日：2014-04-24

申请号：US14145157

申请日：2013-12-31

Applicant: ARM LIMITED

Inventor： Gus YEUNG ,  Martin Jay KINKADE ,  Marlin Wayne FREDERICK, JR.

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract translation: 公开了一种生成集成电路的布局的方法，该布局包括标准单元和由存储器编译器生成的至少一个存储器实例，以定义集成电路的存储器件。 接收指定所需存储器实例的一个或多个属性的输入数据。 内存编译器基于输入数据并使用指定的内存架构生成所需的内存实例。 提供了一个标准的细胞库。 内存编译器引用标准单元库的至少一个属性，以便生成所需的内存实例。 然后通过用从标准单元库中选择的标准单元格填充标准单元行来生成布局，以便提供集成电路所需的功能组件，并将由存储器编译器提供的所需存储器实例集成到布局中。