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公开(公告)号：US10579775B2
公开(公告)日：2020-03-03
申请号：US16033158
申请日：2018-07-11
Applicant: Arm Limited
Inventor： Vincent Philippe Schuppe , Syam Kumar Lalitha Gopalakrishnan Nair , Hongwei Zhu , Neeraj Dogra , Mouli Rajaram Chollangi , Arjun R. Prasad
Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.
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公开(公告)号：US20180173834A1
公开(公告)日：2018-06-21
申请号：US15387460
申请日：2016-12-21
Applicant: ARM Limited
Inventor： Mouli Rajaram Chollangi , Hongwei Zhu , Hemant Joshi , Chandan Kumar Rajendran , Prashant Lokeshwar , Umang Deepak Kumar Doshi , Neeraj Dogra
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F17/5072 , G06F2217/12 , G06F2217/40 , G06F2217/82
Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.
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公开(公告)号：US11567741B2
公开(公告)日：2023-01-31
申请号：US16899502
申请日：2020-06-11
Applicant: Arm Limited
Inventor： Mouli Rajaram Chollangi , Sriram Thyagarajan , Hongwei Zhu , Yew Keong Chong , Pratik Ghanshambhai Satasia
Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.
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公开(公告)号：US20180173822A1
公开(公告)日：2018-06-21
申请号：US15387373
申请日：2016-12-21
Applicant: ARM Limited
Inventor： Hongwei Zhu , Mouli Rajaram Chollangi , Hemant Joshi , Yew Keong Chong , Satinderjit Singh , Betsie Jacob , Neeraj Dogra , Sriram Thyagarajan
CPC classification number: G06F17/5009 , G06F17/30289 , G06F17/5068 , G06F2217/12
Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.
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Patent Agency Ranking
公开(公告)号：US20200019669A1
公开(公告)日：2020-01-16
申请号：US16033158
申请日：2018-07-11
Applicant: Arm Limited
Inventor： Vincent Philippe Schuppe , Syam Kumar Lalitha Gopalakrishnan Nair , Hongwei Zhu , Neeraj Dogra , Mouli Rajaram Chollangi , Arjun R. Prasad
IPC: G06F17/50 , G11C11/412 , H01L27/11 , H01L27/02
Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.
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公开(公告)号：US10296688B2
公开(公告)日：2019-05-21
申请号：US15387460
申请日：2016-12-21
Applicant: ARM Limited
Inventor： Mouli Rajaram Chollangi , Hongwei Zhu , Hemant Joshi , Chandan Kumar Rajendran , Prashant Lokeshwar , Umang Deepak kumar Doshi , Neeraj Dogra
IPC: G06F17/50
Abstract: A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.
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公开(公告)号：US10140399B2
公开(公告)日：2018-11-27
申请号：US15387373
申请日：2016-12-21
Applicant: ARM Limited
Inventor： Hongwei Zhu , Mouli Rajaram Chollangi , Hemant Joshi , Yew Keong Chong , Satinderjit Singh , Betsie Jacob , Neeraj Dogra , Sriram Thyagarajan
Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.
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公开(公告)号：US20210389934A1
公开(公告)日：2021-12-16
申请号：US16899502
申请日：2020-06-11
Applicant: Arm Limited
Inventor： Mouli Rajaram Chollangi , Sriram Thyagarajan , Hongwei Zhu , Yew Keong Chong , Pratik Ghanshambhai Satasia
IPC: G06F8/30 , G06F8/38 , G06F8/71 , G06F16/901
Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.
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公开(公告)号：US10521532B1
公开(公告)日：2019-12-31
申请号：US16125158
申请日：2018-09-07
Applicant: Arm Limited
Inventor： Pratik Ghanshambhai Satasia , Yew Keong Chong , Sriram Thyagarajan , Hongwei Zhu , Mouli Rajaram Chollangi
Abstract: Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.
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