公开(公告)号：US20150178220A1

公开(公告)日：2015-06-25

申请号：US14579483

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Roko GRUBISIC ,  Andrew BURDASS ,  Daren CROXFORD ,  Isidoros SIDERIS

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/304 ,  Y02D10/13

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

Abstract translation: 提供地址转换电路和操作这种翻译电路的方法。 地址转换电路被配置为接收在第一寻址系统中使用的第一地址并将其转换成在第二寻址系统中使用的第二地址。 翻译流水线电路具有多个流水线级，配置成在多个流水线阶段的过程中将第一地址转换为第二地址。 地址比较电路被配置为当接收到的第一地址至少部分匹配先前接收到的第一地址时，识别地址匹配条件。 插入电路被配置为确定多个流水线级中先前接收到的第一地址的进展阶段，并且当地址比较电路识别时，使下一个流水线周期使先前接收的第一地址的进展阶段的内容不变 地址匹配条件。

公开(公告)号：US20240037835A1

公开(公告)日：2024-02-01

申请号：US18362439

申请日：2023-07-31

Applicant: ARM Limited

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Isidoros SIDERIS

IPC: G06T15/00 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60

Abstract: There is provided an apparatus configured to operate as a shader core, the shader core configured to perform a complex rendering process comprising a rendering process and a machine learning process, the shader core comprising: one or more tile buffers configured to store data locally to the shader core, wherein during the rendering process, the one or more tile buffers are configured to store rendered fragment data relating to a tile; and during the machine learning process, the one or more tile buffers are configured to store an input feature map, kernel weights or an output feature map relating to the machine learning process.

公开(公告)号：US20190087928A1

公开(公告)日：2019-03-21

申请号：US16117098

申请日：2018-08-30

Applicant: ARM Limited

Inventor： Stephane FOREY ,  Isidoros SIDERIS ,  Reimar Gisbert DÖFFINGER

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/52

Abstract: A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.

公开(公告)号：US20160110837A1

公开(公告)日：2016-04-21

申请号：US14874829

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Isidoros SIDERIS ,  Michel Patrick Gabriel Emil IWANIEC ,  Andrew BURDASS ,  Nebojsa MAKLJENOVIC ,  Andreas Due ENGH-HALSTVEDT

IPC: G06T1/00 ,  G06T1/60

CPC classification number: G06T11/40 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/005 ,  G06T15/40 ,  G06T15/405 ,  G06T2207/20021

Abstract: A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.

Abstract translation: 提供了执行图形处理的图形处理装置和方法。 图形处理装置包括能够执行图形处理以生成显示数据的帧的处理级的序列。 图形处理以逐个瓦片为基础进行。 图形处理装置能够确定受图形处理影响的当前图块是否为空。 对于当前瓦片的图形处理，根据当前瓦片是否为空，省略处理级序列的至少一个处理级。

公开(公告)号：US20240036949A1

公开(公告)日：2024-02-01

申请号：US18362405

申请日：2023-07-31

Applicant: ARM Limited

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Isidoros SIDERIS

IPC: G06F9/54 ,  G06F9/48 ,  G06F12/0842

CPC classification number: G06F9/542 ,  G06F9/4843 ,  G06F12/0842 ,  G06F2209/543 ,  G06F2212/62 ,  G06F2212/60

Abstract: There is provided a processor configured to transfer data to a plurality of processor circuits. The apparatus includes broadcast circuitry that broadcasts first machine learning data to at least a subset of the plurality of processor circuits.

公开(公告)号：US20190073241A1

公开(公告)日：2019-03-07

申请号：US16044747

申请日：2018-07-25

Applicant: ARM Limited

Inventor： Isidoros SIDERIS ,  Eugenia CORDERO-CRESPO ,  Amir KLEEN

IPC: G06F9/48 ,  G06F9/32 ,  G06F9/30 ,  G06F9/46

Abstract: An apparatus and method are provided for executing thread groups. The apparatus comprises scheduling circuitry for selecting for execution a first thread group from a plurality of thread groups, and thread processing circuitry that is responsive to the scheduling circuitry to execute active threads of the first thread group in dependence on a common program counter shared between the active threads. In response to an exit event occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present, and this can be used to trigger program counter checking circuitry to perform a program counter check operation to update the common program counter and an active thread indication for the first thread group. The thread processing circuitry is provided with register storage in which program counter information for each thread of the first thread group can be stored, and the program counter checking circuitry is arranged to have access to that register storage when performing the program counter check operation. Further, the scheduling circuitry is arranged to select, for execution by the thread processing circuitry, a different thread group whilst awaiting performance of the program counter check operation by the program counter checking circuitry for the first thread group. This provides an area efficient mechanism for handling divergence and re-convergence of threads within thread groups, in a manner that avoids impacting performance.

公开(公告)号：US20150301826A1

公开(公告)日：2015-10-22

申请号：US14663858

申请日：2015-03-20

Applicant: ARM LIMITED

Inventor： Isidoros SIDERIS ,  Daren CROXFORD ,  Andrew BURDASS

IPC: G06F9/30 ,  G06F1/32

Abstract: A data processing apparatus has control circuitry for detecting whether a first micro-operation to be processed by a first processing lane would give the same result as a second micro-operation processed by a second processing lane. if they would give the same result, then the first micro-operation is prevented from being processed by the first processing lane and the result of the second micro-operation is output as the result of the first micro-operation. This avoids duplication of processing, to save energy for example.

Abstract translation: 数据处理装置具有控制电路，用于检测由第一处理车道处理的第一微操作是否将给出与由第二处理车道处理的第二微操作相同的结果。 如果它们给出相同的结果，则防止第一微操作被第一处理通道处理，并且作为第一微操作的结果输出第二微操作的结果。 这避免了重复的处理，以节省能源。

公开(公告)号：US20230062386A1

公开(公告)日：2023-03-02

申请号：US17821666

申请日：2022-08-23

Applicant: Arm Limited

Inventor： Isidoros SIDERIS ,  Péter SONKOLY ,  Adrian Pereiro CASTRO

IPC: G06T15/00 ,  G06F9/38

Abstract: Disclosed is a method of handling thread termination events within a graphics processor when a group of plural execution lanes are executing in a co-operative state. When a group of lanes is in the co-operative state, in response to the graphics processor encountering an event that means that a subset of one or more execution threads associated with the group of execution lanes in the co-operative state should be terminated: it is determined whether a condition to immediately terminate the subset of one or more execution threads is met. When the condition is not met, the group of execution lanes continue their execution in the co-operative state, but a record is stored to track that the threads in the subset of one or more execution threads should subsequently be terminated.

公开(公告)号：US20150301827A1

公开(公告)日：2015-10-22

申请号：US14664241

申请日：2015-03-20

Applicant: ARM LIMITED

Inventor： Isidoros SIDERIS ,  Daren CROXFORD ,  Andrew BURDASS

IPC: G06F9/30 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F9/30181 ,  G06F9/34 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3887 ,  Y02D10/152 ,  Y02D50/20

Abstract: A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by processing circuitry is for the same data processing operation and specifies the same at least one operand as the last valid micro-operation processed by the processing circuitry. If so, then the control circuitry prevents the processing circuitry processing the current micro-operation so that an output register is not updated in response to the current micro-operation, and outputs the current value stored in the output register as the result of the current micro-operation. This allows power consumption to be reduced or performance to be improved by not repeating the same computation.

Abstract translation: 数据处理装置具有控制电路，用于检测由处理电路处理的当前微操作是否用于相同的数据处理操作，并指定与由处理电路处理的最后一个有效微操作相同的至少一个操作数。 如果是这样，则控制电路防止处理电路处理当前的微操作，使得输出寄存器不响应于当前微操作被更新，并且作为电流的结果输出存储在输出寄存器中的当前值 微操作。 这允许通过不重复相同的计算来降低功耗或提高性能。

公开(公告)号：US20150301584A1

公开(公告)日：2015-10-22

申请号：US14663831

申请日：2015-03-20

Applicant: ARM LIMITED

Inventor： Isidoros SIDERIS ,  Daren CROXFORD ,  Andrew BURDASS

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F9/3808 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3869 ,  Y02D10/152

Abstract: A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by a processing pipeline would give the same result as an earlier micro-operation. If so, then the current micro-operation is passed through the processing pipeline, with at least one pipeline stage passed by the current micro-operation being placed in a power saving state during a processing cycle in which the current micro-operation is at that pipeline stage. The result of the earlier micro-operation is then output as a result of said current micro-operation. This allows power consumption to be reduced by not repeating the same computation.

Abstract translation: 数据处理装置具有用于检测由处理流水线处理的当前微操作是否将给出与较早的微操作相同的结果的控制电路。 如果是这样，则当前的微操作通过处理流水线，当前的微操作在当前微操作的处理周期期间，通过当前微操作的至少一个流水线级处于省电状态 流水线阶段 作为所述当前微操作的结果，输出较早的微操作的结果。 这允许通过不重复相同的计算来减少功耗。