公开(公告)号：US09411362B2

公开(公告)日：2016-08-09

申请号：US14193492

申请日：2014-02-28

Applicant: ARM LIMITED

Inventor： Brett Stanley Feero ,  Michael Alan Filippo

IPC: G06F12/00 ,  G06F1/12 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F1/12 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0835 ,  G06F2212/1028

Abstract: A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronization circuitry then receives the write pointer and synchronizes the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer. However, for a read operation to be performed, it is necessary that the synchronized write pointer indication indicates that there is a data value written into the storage structure that is available to be read. Early update circuitry is configured, for a write operation, to alter the write pointer indication provided to the write pointer synchronization circuitry a number of clock cycles of the first clock domain before the write operation is performed. That number of clock cycles is chosen dependent on the difference in clock speed between the first clock domain and the second clock domain, and the predetermined number of clock cycles of the second clock domain taken by the write pointer synchronization circuitry to synchronize the write pointer indication to the second clock domain. Such an approach enables at least a part of the latency of the write pointer synchronization circuitry to be hidden, thereby improving performance of the storage circuitry.

Abstract translation: 提供了一种用于在第一时钟域和第二时钟域之间的时钟边界上传播数据值的存储电路和方法。 存储结构设置有至少一个条目，并且写入电路在第一时钟域中执行写入操作，其中每个写入操作将数据值写入由写入指针识别的存储结构的条目中。 写入电路在每个写操作之间改变写指针。 写指针同步电路然后接收写指针，并在第二时钟域的预定数量的时钟周期上使写指针指示与第二时钟域同步。 读取电路在第二时钟域中执行读取操作，每次读取操作从读取指针识别的存储结构的条目读取数据值。 然而，对于要执行的读操作，同步的写指针指示必须指示存储有可读取的存储结构中的数据值。 早期更新电路被配置为用于写入操作，以在执行写入操作之前改变提供给写指针同步电路的写入指针指示第一时钟域的多个时钟周期。 根据第一时钟域和第二时钟域之间的时钟速度的差异以及由写指针同步电路取得的第二时钟域的预定数量的时钟周期来选择该数量的时钟周期，以使写指针指示 到第二个时钟域。 这种方法使得写指针同步电路的等待时间的至少一部分能够被隐藏，从而提高存储电路的性能。

公开(公告)号：US10289417B2

公开(公告)日：2019-05-14

申请号：US14519697

申请日：2014-10-21

Applicant: ARM LIMITED

Inventor： Michael Alan Filippo ,  Matthew Paul Elwood ,  Umar Farooq ,  Adam George

IPC: G06F9/30 ,  G06F9/38

Abstract: A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.

公开(公告)号：US09600179B2

公开(公告)日：2017-03-21

申请号：US14446668

申请日：2014-07-30

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C8/08 ,  G06F3/06 ,  G06F1/32 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22

CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

公开(公告)号：US09542194B2

公开(公告)日：2017-01-10

申请号：US14482146

申请日：2014-09-10

Applicant: ARM LIMITED

Inventor： Chris Abernathy ,  Florent Begon ,  Michael Alan Filippo

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/384

Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.

Abstract translation: 单线程无序处理器2包括架构化寄存器文件22和推测寄存器文件20.推测性寄存器分配电路24用于根据分配序列分配推测寄存器，并从由尾部确定的位置 点。 读取抑制电路30用于维持与分配序列内的位置相对应的边界指针，使得在分配序列内最近不再分配比与边界指针对应的推测寄存器可以具有有效的寄存器值。 读取抑制电路30用于抑制位于由尾点和边界指针限定的读取抑制区域内的源操作数的读取操作。 可以为不同类型的寄存器值保持单独的边界指针，例如整数寄存器值和浮点寄存器值。

公开(公告)号：US20160034403A1

公开(公告)日：2016-02-04

申请号：US14446668

申请日：2014-07-30

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G06F12/08

CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

Abstract translation: 提供了存储器件和操作存储器件的方法。 存储器件包括多个存储单元和访问控制电路。 访问控制被配置为接收访问请求并且响应于访问请求以在多个存储单元中的每一个中发起访问过程。 所述访问控制电路被配置为在所述访问过程已经被启动之后接收访问终止信号，并且响应于所述访问禁止信号来启动访问抑制以抑制所述多个存储单元中的至少一个中的访问过程。 因此，通过响应于访问请求在所有存储单元中启动访问过程，例如， 在不等待对其进行访问过程的特定存储单元的进一步指示的情况下，存储器件的总访问时间保持为低，但是通过使访问过程中的至少一个随后能够被响应于访问被抑制 杀死信号动态功耗的存储器件可以减少。