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1.发明授权公开(公告)号：US10747647B2
公开(公告)日：2020-08-18
申请号：US16063802
申请日：2015-12-22
Applicant: ARM LIMITED
Inventor： Damien Robin Martin , Clément Marc Demongeot , Michael John Williams
Abstract: A method, apparatus and system are provided for diagnosing a processor executing a stream of instructions by causing the processor to execute the stream of instructions in a sequence of stages with a diagnostic exception being taken between each stage. The method involves controlling the processor in a current stage, when a point is reached where the diagnostic exception is to be taken, to store in a storage location type indicator information comprising a type indicator for a current instruction in the stream and a type indicator for a next instruction in the stream. The diagnostic exception is then taken, causing a diagnostic operation to be performed which includes accessing the type indicator information from the storage location and, dependent on the type indicator for the current instruction and the type indicator for the next instruction, determining control information to identify at least one trigger condition for a next diagnostic exception. Thereafter, return from the diagnostic exception causes the processor to operate in a next stage in accordance with the determined control information. By capturing information not only about the current instruction being processed at the point that the diagnostic exception is to be taken, but also information about the next instruction, this can provide a significant improvement in the efficiency of the handling of the diagnostic process.
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公开(公告)号：US10606679B2
公开(公告)日：2020-03-31
申请号：US15830380
申请日：2017-12-04
Applicant: Arm Limited
Inventor： Anitha Kona , Michael John Williams , John Michael Horley , Alasdair Grant
Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.
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公开(公告)号：US10318407B2
公开(公告)日：2019-06-11
申请号：US15140514
申请日：2016-04-28
Applicant: ARM Limited
Inventor： Michael John Williams , Richard Roy Grisenthwaite , Simon John Craske
IPC: G06F9/318 , G06F11/267 , G06F11/36 , G06F9/455 , G06F9/30
Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.
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公开(公告)号：US10228942B2
公开(公告)日：2019-03-12
申请号：US15532286
申请日：2015-11-23
Applicant: ARM LIMITED
Inventor： Michael John Williams , John Michael Horley , Stephan Diestelhorst
Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.
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5.发明授权公开(公告)号：US09858172B2
公开(公告)日：2018-01-02
申请号：US15007578
申请日：2016-01-27
Applicant: ARM LIMITED
Inventor： Michael John Williams
CPC classification number: G06F11/3636 , G06F11/3644
Abstract: An apparatus and method are provided for controlling debugging of program instructions that include a transaction, where the transaction is executed on processing circuitry and comprises a number of program instructions that execute to generate updates to state data, and where those updates are only committed if the transaction completes without a conflict. In addition to the processing circuitry, the apparatus has control storage for storing at least one watchpoint identifier, and the processing circuitry is then arranged, when detecting a watchpoint match condition with reference to the at least one watchpoint identifier during execution of a program instruction within the transaction, to create a pending watchpoint debug event. The processing circuitry is then responsive to execution of the transaction finishing to initiate a watchpoint debug event for the pending watchpoint debug event. However, if instead the transaction is aborted before it finishes (due to a conflict arising), the processing circuitry is arranged to cancel the pending watchpoint debug event. Such an approach prevents a probe effect arising during execution of a transaction due to debugging activity.
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Patent Agency Ranking
公开(公告)号：US09652348B2
公开(公告)日：2017-05-16
申请号：US14824299
申请日：2015-08-12
Applicant: ARM LIMITED
Inventor： Michael John Williams , Simon John Craske
CPC classification number: G06F11/26 , G06F9/30189 , G06F11/2236 , G06F11/3648
Abstract: A data processing apparatus has a debug state in which processing circuitry 105 executes instructions received from the debug interface 115. Control changing circuitry 135 prohibits the execution of instructions in a predefined privilege mode when in the debug state if a control parameter has a predefined value. In response to a first exception being signalled while in the debug state, where the first exception is intended to be handled at the predefined privilege mode, and further in response to the control parameter having the predefined value, signalling circuitry 115 signals a second exception to be handled at a different privilege mode from the predefined privilege mode and sets information identifying a type of the first exception. Consequently, without having to enter the prohibited (predefined) privilege mode, the debugger 110 can be made aware of the first exception that would ordinarily be handled at the predefined, i.e. prohibited privilege mode.
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公开(公告)号：US12189511B2
公开(公告)日：2025-01-07
申请号：US18007233
申请日：2021-08-02
Applicant: ARM LIMITED
Inventor： Michael John Williams
Abstract: A data processing apparatus and method having processing circuitry, and trace circuitry having a trace buffer; write pointer storage, and a call depth counter, wherein the trace circuitry generates trace data processing first event activities: modify the call depth counter in a first direction, store first trace data indicative of the first event, and modify the write pointer to point to a next location in the trace buffer; in response to a second event, when the call depth counter is not equal to a threshold call depth, to: modify the call depth counter direction and the write pointer to point to a previous location in the trace buffer; and in response to the second event, when the call depth counter is equal to the threshold call depth, to store second trace data indicative of the second event in the trace buffer at the current location.
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公开(公告)号：US20240403190A1
公开(公告)日：2024-12-05
申请号：US18697460
申请日：2022-08-11
Applicant: Arm Limited
Inventor： Michael John Williams
Abstract: An apparatus comprises reset circuitry to perform a cold reset and to perform a warm reset by resetting a subset of state that is reset the cold reset, and branch recording circuitry to perform branch recording to store, in branch record storage circuitry, information about processed branch instructions. The branch recording circuitry determines whether warm and cold branch recording configuration values held in at least one register satisfy a predetermined condition; and when the warm and cold branch recording configuration values fail to satisfy the predetermined condition, branch recording is disabled. The branch record storage circuitry is configured to make the information about the processed branch instruction available for diagnostic analysis. The cold reset comprises resetting both of the warm and cold branch recording configuration values, and the warm reset comprises resetting the warm branch recording configuration value and leaving the cold branch recording configuration value unchanged.
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公开(公告)号：US12099445B2
公开(公告)日：2024-09-24
申请号：US18320407
申请日：2023-05-19
Applicant: Arm Limited
Inventor： Michael John Williams , John Michael Horley
IPC: G06F12/0815
CPC classification number: G06F12/0815
Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.
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公开(公告)号：US11436124B2
公开(公告)日：2022-09-06
申请号：US16966981
申请日：2019-01-17
Applicant: Arm Limited
Inventor： Michael John Williams , John Michael Horley
Abstract: To access metadata when debugging a device, debug access port circuitry including a debug interface receives commands from a debugger, and a bus interface coupled to a bus enables the debugger to access a memory system of the device. The device operates on data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus. The debug access port circuitry has storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. A metadata storage element stores metadata items, and the debug access port circuitry is responsive to a command from the debugger to perform a memory direct access to transfer metadata items between the metadata storage element and the memory system.
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