公开(公告)号：US20190163902A1

公开(公告)日：2019-05-30

申请号：US16149297

申请日：2018-10-02

Applicant: Arm Limited

Inventor： Alastair David REID ,  Dominic Phillip MULLIGAN ,  Milosch MERIAC ,  Matthias Lothar BOETTCHER ,  Nathan Yong Seng CHONG ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Frederic Claude Marie PIRY ,  Albin Pierrick TONNERRE ,  Thomas Christopher GROCUTT ,  Yasuo ISHII

IPC: G06F21/55 ,  H04L9/06 ,  G06F12/10 ,  G06F9/38

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

公开(公告)号：US20210279124A1

公开(公告)日：2021-09-09

申请号：US17261217

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Emre ÖZER ,  Xabier ITURBE ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

公开(公告)号：US20190391888A1

公开(公告)日：2019-12-26

申请号：US16014154

申请日：2018-06-21

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Xabier ITURBE ,  Emre OZER ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/20 ,  G06F11/14 ,  G06F11/16

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

公开(公告)号：US20180026799A1

公开(公告)日：2018-01-25

申请号：US15549505

申请日：2016-01-25

Applicant: ARM IP Limited ,  ARM LIMITED

Inventor： Remy POTTIER ,  Amyas Edward Wykes PHILLIPS ,  Milosch MERIAC

IPC: H04L9/32 ,  H04L9/14 ,  H04L9/30

CPC classification number: H04L9/3263 ,  H04L9/14 ,  H04L9/30 ,  H04L9/3226 ,  H04L9/3247 ,  H04L9/3265 ,  H04L9/3271 ,  H04L63/0823

Abstract: There is disclosed a method of establishing trust between an agent device and a verification apparatus, the method comprising: obtaining, at the agent device, a trust credential, wherein the trust credential relates to an aspect of the agent device and comprises authentication information for identifying at least one party trusted by the verification apparatus and/or device data relating to the agent device; transmitting, from the agent device to the verification apparatus, the trust credential; obtaining, at the verification apparatus, the trust credential; analysing, at the verification apparatus, the trust credential; determining, at the verification apparatus, whether the agent device is trusted based on the analysis; and responsive to determining the agent device is trusted, establishing trust between the agent device and the verification apparatus.

公开(公告)号：US20180365449A1

公开(公告)日：2018-12-20

申请号：US16060116

申请日：2016-12-02

Applicant: ARM Limited

Inventor： Milosch MERIAC ,  Alessandro Angelino

IPC: G06F21/74 ,  H04L9/08 ,  H04L29/06

Abstract: A device comprising: a processing element; a data store, coupled to the processing element, the data store comprising a non-volatile data store having a trusted region for trusted code and an untrusted region for untrusted code; a security component, coupled to the processing element and the data store, wherein the security component is configured to, in response to one of a power event occurring at the device and receiving a trigger signal, send a first signal to the processing element and the data store, and wherein the processing element is configured to execute trusted code in response to the first signal.

公开(公告)号：US20190370130A1

公开(公告)日：2019-12-05

申请号：US15995469

申请日：2018-06-01

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Shidhartha DAS

IPC: G06F11/16 ,  G06F1/12

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

公开(公告)号：US20180136984A1

公开(公告)日：2018-05-17

申请号：US15572692

申请日：2016-04-21

Applicant: ARM IP LIMITED ,  ARM LIMITED

Inventor： Christopher Mark PAOLA ,  Milosch MERIAC ,  Remy POTTIER

IPC: G06F9/50 ,  H04L29/08 ,  G06F11/34

CPC classification number: G06F9/5088 ,  G06F11/34 ,  G06F11/3409 ,  G06F11/3442 ,  H04L67/10 ,  H04L67/1008 ,  H04L67/327

Abstract: A system provided at nodes within a network of nodes enabling the nodes to migrate activities to other nodes within its communication range to provide load balancing across the network. The other nodes having power and processing capabilities and capacity enabling them to undertake the migrated activities.