公开(公告)号：US20160078252A1

公开(公告)日：2016-03-17

申请号：US14486181

申请日：2014-09-15

Applicant: ARM LIMITED

Inventor： Vikas CHANDRA ,  Robert Campbell AITKEN

IPC: G06F21/79 ,  H04L9/08 ,  G06F21/72 ,  G06F12/14

CPC classification number: G06F12/1408 ,  G06F21/72 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/402 ,  G09C1/00 ,  H04L9/0861 ,  H04L9/0866 ,  H04L2209/12

Abstract: Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Abstract translation: 存储器6内的数据加密由密钥生成电路12提供，该密钥生成电路12用于生成作为被访问的存储器6内的地址的函数的密钥，然后分别用于加密或解密数据的加密电路14或解密电路16 作为基于地址生成的密钥的函数。 可以使用按位异或运算来执行加密和解密。 密钥生成电路可以具有物理上不可克隆的功能电路的形式，其从实例到实现实例变化，并且在相同的实例中的写入和读取操作两者之间，为同一地址生成相同的密钥。

公开(公告)号：US20150363267A1

公开(公告)日：2015-12-17

申请号：US14306697

申请日：2014-06-17

Applicant: ARM Limited

Inventor： Vikas CHANDRA ,  Robert Campbell AITKEN

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318519 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/3187 ,  G06F1/08 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1032 ,  G06F11/1048 ,  G11C11/419

Abstract: A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.

Abstract translation: 提供一种具有多个数据存储单元的数据存储装置，每个数据存储单元被配置为存储数据字的相应数据位。 存储的数据值奇偶校验生成电路被配置为根据存储在多个数据存储单元中的数据字的数据位产生数据字的奇偶校验位。 存储的数据值奇偶校验生成电路被配置为使得当从多个数据存储单元读出数据字时，不会发生存储的数据值奇偶校验生成电路内的切换。 转换检测电路被配置为检测奇偶校验位的值的变化。

公开(公告)号：US20170046281A1

公开(公告)日：2017-02-16

申请号：US15335479

申请日：2016-10-27

Applicant: ARM LIMITED

Inventor： Vikas CHANDRA ,  Robert Campbell AITKEN

IPC: G06F12/14 ,  H04L9/08 ,  G09C1/00 ,  G06F21/72 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F21/72 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/402 ,  G09C1/00 ,  H04L9/0861 ,  H04L9/0866 ,  H04L2209/12

Abstract: Encryption of data within a memory is provided by key generation circuitry which serves to generate a key as a function of the address within the memory being accessed and then encryption circuitry or decryption circuitry which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Abstract translation: 由存储器内的地址的函数产生密钥的密钥生成电路提供存储器内的数据加密，然后分别用于加密或解密数据作为函数的加密电路或解密电路 基于地址生成的密钥。 可以使用按位异或运算来执行加密和解密。 密钥生成电路可以具有物理上不可克隆的功能电路的形式，其从实例到实现实例变化，并且在相同的实例中的写入和读取操作两者之间，为同一地址生成相同的密钥。

公开(公告)号：US20150371718A1

公开(公告)日：2015-12-24

申请号：US14310162

申请日：2014-06-20

Applicant: ARM LIMITED

Inventor： Alan Jeremy BECKER ,  Chiloda Ashan Senerath PATHIRANE ,  Robert Campbell AITKEN

IPC: G11C29/14

CPC classification number: G11C29/14 ,  G06F11/008 ,  G11C29/16 ,  G11C2029/0409

Abstract: A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.

Abstract translation: 数据处理装置具有至少一个存储器和处理电路。 存储器内置自检（MBIST）接口接收MBIST请求，指示要执行测试程序来测试至少一个目标存储器位置。 控制电路检测MBIST请求并保留用于测试至少一个保留的存储器位置，包括目标存储器位置。 在测试过程期间，存储器继续服务处理电路所发出的存储器事务，该处理电路针对存储器位置而不是由控制电路保留的保留位置。 如果处理电路尝试访问保留的存储器位置，则停止处理。 测试包括不经常发生的短突发事件。 这样，当处理器在现场运行时，MBIST测试可能会持续下去，从而降低性能影响。