公开(公告)号：US20210249070A1

公开(公告)日：2021-08-12

申请号：US16786779

申请日：2020-02-10

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Disha Singh ,  Gautam Garg ,  Srinivasan Srinath ,  Georgy Jacob

IPC: G11C11/418 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

公开(公告)号：US20220415385A1

公开(公告)日：2022-12-29

申请号：US17897716

申请日：2022-08-29

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Disha Singh ,  Gautam Garg ,  Srinivasan Srinath ,  Georgy Jacob

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

公开(公告)号：US09407265B2

公开(公告)日：2016-08-02

申请号：US14088570

申请日：2013-11-25

Applicant: ARM LIMITED

Inventor： Srinivasan Srinath ,  Ambica Ashok ,  Fakhruddin Ali Bohra

IPC: H03K19/096 ,  H03K19/017 ,  H03K19/00 ,  H03K19/094 ,  G11C11/419 ,  G11C7/12

CPC classification number: H03K19/01721 ,  G11C7/12 ,  G11C11/419 ,  H03K19/0013 ,  H03K19/09429 ,  H03K19/0963

Abstract: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.

Abstract translation: 集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。 信号辅助电路包括第一和第二辅助电路。 第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑 下拉转换后的低信号电平。 通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。

公开(公告)号：US08963609B2

公开(公告)日：2015-02-24

申请号：US13782120

申请日：2013-03-01

Applicant: ARM Limited

Inventor： Gus Yeung ,  Srinivasan Srinath ,  Fakhruddin Ali Bohra

IPC: H03L5/00

CPC classification number: H03K19/0185

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching.

Abstract translation: 集成电平移位组合电路在第一电压域中接收多个输入信号，并执行组合操作以在第二电压域中产生输出信号。 电路包括组合电路，其包括在相应的第一和第二电压域中操作的第一组合电路部分和第二组合电路部分。 第二组合电路部分具有输出节点，其电压电平标识输出信号的值，并且包括对由第一组合电路部分产生的中间信号施加电平移位功能的反馈电路。 在组合电路的组合操作的性能导致组合电路切换输出节点上的电压的情况下，争用减轻电路减少了反馈电路内的至少一个组件上的电压降，争用缓解电路因此有助于组合电路 在输出节点电压切换。

公开(公告)号：US11830542B2

公开(公告)日：2023-11-28

申请号：US17897716

申请日：2022-08-29

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Disha Singh ,  Gautam Garg ,  Srinivasan Srinath ,  Georgy Jacob

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

公开(公告)号：US11430506B2

公开(公告)日：2022-08-30

申请号：US16786779

申请日：2020-02-10

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Disha Singh ,  Gautam Garg ,  Srinivasan Srinath ,  Georgy Jacob

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.