公开(公告)号：US09686104B2

公开(公告)日：2017-06-20

申请号：US14833427

申请日：2015-08-24

Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Inventor： Amir Eliaz ,  Ilan Reuven

IPC: H04L25/03 ,  H04L1/00 ,  H04M11/06 ,  H04L27/38 ,  H04L25/06

CPC classification number: H04L25/03286 ,  H04L1/005 ,  H04L1/0054 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03305 ,  H04L25/03318 ,  H04L25/067 ,  H04L27/38 ,  H04M11/06 ,  H04M11/062

Abstract: A receiver comprises a sequence estimation circuit and a soft-input-soft-output (SISO) decoder. The sequence estimation circuit comprises circuitry operable to generate first soft bit decisions for symbols of a received inter-symbol-correlated signal. The SISO decoder comprises circuitry operable to decode the first soft bit decisions to generate corrected soft bit decisions. The circuitry of the sequence estimation circuit is operable to generate, based on the corrected soft bit decisions, second soft bit decisions for the symbols of the received inter-symbol-correlated signal, which are improved/refined relative to the first soft bit decisions.

公开(公告)号：US09800447B2

公开(公告)日：2017-10-24

申请号：US14951579

申请日：2015-11-25

Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Inventor： Amir Eliaz ,  Ilan Reuven

IPC: H04L25/497 ,  H04L27/34 ,  H04L27/26 ,  H04L25/03 ,  H04L1/00 ,  H04L25/02

CPC classification number: H04L27/2628 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03038 ,  H04L25/03159 ,  H04L25/03197 ,  H04L25/03821 ,  H04L25/497 ,  H04L27/2647 ,  H04L27/3405 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03522

Abstract: A transmitter may comprise a symbol mapper circuit and operate in at least two modes. In a first mode, the number of symbols output by the mapper circuit per orthogonal frequency division multiplexing (OFDM) symbol transmitted by said transmitter may be greater than the number of data-carrying subcarriers used to transmit the OFDM symbol. In a second mode, the number of symbols output by said mapper circuit per orthogonal frequency division multiplexing (OFDM) symbol transmitted by said transmitter is less than or equal to the number of data-carrying subcarriers used to transmit said OFDM symbol. The symbols output by the symbol mapper circuit may be N-QAM symbols. While the circuitry operates in the first mode, the symbols output by the mapper may be converted to physical subcarrier values via filtering and decimation prior to being input to an IFFT circuit.

公开(公告)号：US20170141875A1

公开(公告)日：2017-05-18

申请号：US15340571

申请日：2016-11-01

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Amir ELIAZ ,  Ilan Reuven ,  Daniel Stopler ,  Roy Oren ,  Shimon Benjo

IPC: H04L1/00 ,  H04W72/08 ,  H04W72/04 ,  H04W8/22

CPC classification number: H04L1/0006 ,  H04L1/0003 ,  H04L1/0018 ,  H04W8/22

Abstract: A device includes circuitry configured to determine one or more signal processing capabilities of another device in communication with the device. The device configures a signal compression mode of the device to correspond to a first signal compression mode of a plurality signal compression modes based on the one or more signal processing capabilities of the other device. The device s configured to modify, in response to detecting variations in one or more network configuration properties or the one or more signal processing capabilities of the other device, the signal compression mode of the device.