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公开(公告)号：US06604184B2
公开(公告)日：2003-08-05
申请号：US09344267
申请日：1999-06-30
IPC分类号： G06F1200
CPC分类号： G06F12/1009
摘要： The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.
摘要翻译： 本发明是一种映射虚拟存储器空间的方法和装置。 区域寄存器文件为虚拟存储器空间中的虚拟地址提供区域标识符。 虚拟地址包括虚拟区号和虚拟页号。 虚拟页表查找电路耦合到区域寄存器文件以从虚拟地址参数生成页表项（PTE）虚拟地址。 虚拟地址参数包括虚拟地址。
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公开(公告)号：US06728858B2
公开(公告)日：2004-04-27
申请号：US09894529
申请日：2001-06-27
申请人： Thomas E. Willis , Achmed R. Zahir
发明人： Thomas E. Willis , Achmed R. Zahir
IPC分类号： G06F1208
CPC分类号： G06F12/1027 , G06F2212/656
摘要： A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.
摘要翻译： 这里公开了一种使用翻译后备缓冲器（TLB）将虚拟地址转换成物理地址的多个逻辑处理器的共享机制。 该机制支持在逻辑处理器之间共享TLB条目，这可以共享地址空间。 该机制还支持逻辑处理器中的私有TLB条目，每个逻辑处理器可以通过相同的虚拟地址访问不同的物理地址。 共享机制提供TLB条目作为私有条目或作为共享条目透明地安装和更新，而不需要特殊的操作系统支持或修改。 可以通过比较逻辑处理器的页表物理基地址来确定逻辑处理器的虚拟地址转换的可靠性。 使用所公开的共享机制，提供快速高效的虚拟地址转换，而不需要更昂贵的功能冗余。
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公开(公告)号：US06353805B1
公开(公告)日：2002-03-05
申请号：US09056451
申请日：1998-04-07
申请人： Achmed R. Zahir , Vincent E. Hummel , Ralph M. Kling , Tse-Yu Yeh
发明人： Achmed R. Zahir , Vincent E. Hummel , Ralph M. Kling , Tse-Yu Yeh
IPC分类号： G06F1100
CPC分类号： G06F9/3867 , G06F11/3466
摘要： An apparatus and method for cycle accounting for a microprocessor are disclosed, in which a performance monitor includes a plurality of silos, a prioritizer, and a combiner. The silos receive delay reason signals from the main processor pipeline, and output staged signals. The prioritizer receives the staged signals, and outputs a plurality of prioritized signals. The combiner selectively combines various of the prioritize signals, and provides signals indicative of microprocessor performance. Each silo includes, in series, a plurality of stages, with each stage containing a single latch. The stages of the silo are synchronized with the stages of the main processor pipeline. The performance monitor operates in real-time, at the same frequency as the microprocessor, and in parallel to the main processor pipeline, and correctly accounts for buffering effects of decoupling buffers. Outputted signals include various signals indicative of microprocessor performance, for example, cache misses, branch mispredictions, and so forth, but only for those miss-events that contribute to a program's visible delay, thereby providing an accurate picture of where cycles are being wasted.
摘要翻译： 公开了一种用于微处理器的循环计费的装置和方法，其中性能监视器包括多个孤岛，优先化器和组合器。 筒仓从主处理器管线接收延迟原因信号，并输出分段信号。 优先级分配器接收分级信号，并输出多个优先级信号。 组合器选择性地组合各种优先级信号，并提供指示微处理器性能的信号。 每个筒仓串联包括多个阶段，每个阶段包含单个闩锁。 筒仓的阶段与主处理器管线的阶段同步。 性能监视器以与微处理器相同的频率实时运行，并且与主处理器管道并行，并且正确地解释了去耦缓冲器的缓冲效应。 输出信号包括指示微处理器性能的各种信号，例如高速缓存未命中，分支错误预测等，但是仅用于有助于程序的可见延迟的那些未命中事件，从而提供了浪费周期的准确图像。
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公开(公告)号：US6052802A
公开(公告)日：2000-04-18
申请号：US1309
申请日：1997-12-31
申请人： Achmed R. Zahir , Vincent E. Hummel , Ralph M. Kling , Tse-Yu Yeh
发明人： Achmed R. Zahir , Vincent E. Hummel , Ralph M. Kling , Tse-Yu Yeh
CPC分类号： G06F9/3867 , G06F11/3466
摘要： An apparatus and method for cycle accounting for a microprocessor are disclosed, in which a performance monitor includes a plurality of silos, a prioritizer, and a combiner. The silos receive delay reason signals from the main processor pipeline, and output staged signals. The prioritizer receives the staged signals, and outputs a plurality of prioritized signals. The combiner selectively combines various of the prioritize signals, and provides signals indicative of microprocessor performance. Each silo includes, in series, a plurality of stages, with each stage containing a single latch. The stages of the silo are synchronized with the stages of the main processor pipeline. The performance monitor operates in real-time, at the same frequency as the microprocessor, and in parallel to the main processor pipeline. Outputted signals include various signals indicative of microprocessor performance, for example, cache misses, branch mispredictions, and so forth, but only for those miss-events that contribute to a program's visible delay, thereby providing an accurate picture of where cycles are being wasted.
摘要翻译： 公开了一种用于微处理器的循环计费的装置和方法，其中性能监视器包括多个孤岛，优先化器和组合器。 筒仓从主处理器管线接收延迟原因信号，并输出分段信号。 优先级分配器接收分级信号，并输出多个优先级信号。 组合器选择性地组合各种优先级信号，并提供指示微处理器性能的信号。 每个筒仓串联包括多个阶段，每个阶段包含单个闩锁。 筒仓的阶段与主处理器管线的阶段同步。 性能监视器以与微处理器相同的频率实时运行，并与主处理器管道并行运行。 输出信号包括指示微处理器性能的各种信号，例如高速缓存未命中，分支错误预测等，但是仅用于有助于程序的可见延迟的那些未命中事件，从而提供了浪费周期的准确图像。
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5.发明申请公开(公告)号：US20140189187A1
公开(公告)日：2014-07-03
申请号：US13732955
申请日：2013-01-02
IPC分类号： G06F13/16
CPC分类号： G06F13/385 , G06F2213/3852
摘要： Methods and apparatus for integrating ARM-based IPs in computer system employing PCI-based fabrics. An PCI-based fabric is operatively coupled to an ARM-based ecosystem employing an ARM-based fabric such as OCP, AHB, or BVCI via a corresponding fabric-to-fabric bridge. Transactions between IP operatively coupled to the PCI-based fabric and IP in the ARM-based ecosystem are facilitated by applying applicable ordering and conversions operations via the fabric-to-fabric bridge and/or fabrics. For example, posted writes originating from IP coupled to the PCI-based fabric are converted to non-posted writes and serialized via the fabric-to-fabric bridge and forwarded to the ARM-based ecosystem.
摘要翻译： 在基于PCI的架构的计算机系统中集成基于ARM的IP的方法和设备。 基于PCI的架构通过相应的Fabric-to-Fabric桥接器可操作地耦合到采用基于ARM的架构（例如OCP，AHB或BVCI）的基于ARM的生态系统。 通过应用适用的排序和转换操作，通过织物到织物桥和/或织物，可以有助于在操作上耦合到基于ARM的基于ARM的结构和IP之间的IP交易。 例如，源自耦合到基于PCI的结构的IP的发布的写入被转换为非发布的写入，并经由Fabric-to-fabric桥序列化并转发到基于ARM的生态系统。
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公开(公告)号：US08943257B2
公开(公告)日：2015-01-27
申请号：US13249414
申请日：2011-09-30
CPC分类号： G06F13/4027 , G06F13/20 , G06F13/385 , G06F13/404 , G06F13/42 , G06F13/4221
摘要： An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.
摘要翻译： 一个实施例将非PCI兼容设备与PCI兼容的操作系统集成。 织物系统模拟PCI的行为。 当非PCI兼容设备不知道如何响应PCI枚举时，实施例提供PCI枚举应答，并因此模拟在仿真期间通常来自PCI兼容设备的应答。 实施例允许系统设计者将非标准结构结构融入到仍然使用在调制解调器PCI兼容的操作系统中发现的稳健且成熟的PCI基础设施的优点。 更一般地，实施例允许符合第一标准（但不是第二标准）的操作系统发现并与不符合第一标准（但可能符合第二标准）的设备进行通信。 本文描述了其它实施例。
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公开(公告)号：US07165164B2
公开(公告)日：2007-01-16
申请号：US10670637
申请日：2003-09-24
申请人： Thomas E. Willis , Achmed R. Zahir
发明人： Thomas E. Willis , Achmed R. Zahir
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/656
摘要： A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.
摘要翻译： 这里公开了一种使用翻译后备缓冲器（TLB）将虚拟地址转换成物理地址的多个逻辑处理器的共享机制。 该机制支持在逻辑处理器之间共享TLB条目，这可以共享地址空间。 该机制还支持逻辑处理器中的私有TLB条目，每个逻辑处理器可以通过相同的虚拟地址访问不同的物理地址。 共享机制提供TLB条目作为私有条目或作为共享条目透明地安装和更新，而不需要特殊的操作系统支持或修改。 可以通过比较逻辑处理器的页表物理基地址来确定逻辑处理器的虚拟地址转换的可靠性。 使用所公开的共享机制，提供快速高效的虚拟地址转换，而不需要更昂贵的功能冗余。
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公开(公告)号：US07073044B2
公开(公告)日：2006-07-04
申请号：US09823472
申请日：2001-03-30
申请人： Thomas E. Willis , Achmed R. Zahir
发明人： Thomas E. Willis , Achmed R. Zahir
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Through use of the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.
摘要翻译： 这里公开了一种共享机制，用于使用翻译后备缓冲器（TLB）的多个逻辑处理器将虚拟地址例如转换成物理地址。 该机制支持在逻辑处理器之间共享TLB条目，这可以共享地址空间。 该机制还支持逻辑处理器中的私有TLB条目，其例如可以通过相同的虚拟地址访问不同的物理地址。 共享机制提供TLB条目作为私有条目或作为共享条目透明地安装和更新，而不需要特殊的操作系统支持或修改。 通过使用所公开的共享机制，提供快速有效的虚拟地址转换，而不需要更昂贵的功能冗余。
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9.发明授权Method and apparatus for transferring data between a register stack and a memory resource 失效用于在寄存器堆栈和存储器资源之间传送数据的方法和装置公开(公告)号：US06263401B1
公开(公告)日：2001-07-17
申请号：US08940834
申请日：1997-09-30
IPC分类号： G06F9315
CPC分类号： G06F9/463 , G06F9/30105 , G06F9/30127 , G06F9/30134
摘要： A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.
摘要翻译： 描述了一种用于将寄存器堆栈中的通用寄存器的内容传送到主存储器中的后备存储器中的位置的计算机实现的方法和装置。 当将通用寄存器的内容传送到后备存储器中的位置时，本发明提出收集临时收集寄存器中预定寄存器组的每个通用寄存器中包含的属性位。 一旦临时收集寄存器被填写，该寄存器的内容将被写入后备存储中的下一个可用位置。 类似地，在从后台存储器恢复寄存器时，保存在后备寄存器中的属性位的集合被传送到临时收集寄存器。 此后，每个属性位与相关联的数据一起保存到通用寄存器中，从而恢复每个通用寄存器的前一个内容。
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公开(公告)号：US20130086287A1
公开(公告)日：2013-04-04
申请号：US13249414
申请日：2011-09-30
CPC分类号： G06F13/4027 , G06F13/20 , G06F13/385 , G06F13/404 , G06F13/42 , G06F13/4221
摘要： An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.
摘要翻译： 一个实施例将非PCI兼容设备与PCI兼容的操作系统集成。 织物系统模拟PCI的行为。 当非PCI兼容设备不知道如何响应PCI枚举时，实施例提供PCI枚举应答，并因此模拟在仿真期间通常来自PCI兼容设备的应答。 实施例允许系统设计者将非标准结构结构融入到仍然使用在调制解调器PCI兼容的操作系统中发现的稳健而成熟的PCI基础设施的优点。 更一般地，实施例允许符合第一标准（但不是第二标准）的操作系统发现并与不符合第一标准（但可能符合第二标准）的设备进行通信。 本文描述了其它实施例。
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