摘要:
An apparatus of a computing node of a computing network, a method to be performed at the apparatus, one or more computer-readable storage media storing instructions to be implemented at the apparatus, and a system including the apparatus. The apparatus includes a processing circuitry to: receive, from an orchestration block, a first workload (WL) package including a WL and first computing resource (CR) metadata; recompose the first WL package into a second WL package that includes the WL and second CR metadata that is different from the first CR metadata, is based at least in part on CR information regarding a server architecture onto which the WL is to be deployed, and is further to indicate one or more processors of the server architecture onto which the WL is to be deployed; and send the second WL package to one or more processors of the server architecture for deployment of the WL thereon.
摘要:
Technologies for performing switch-based collective operations in a fabric architecture include a computing node that includes a host fabric interface (HFI) usable to communicate with network computing devices of the fabric architecture. The HFI is configured to associate an object with a transaction identifier generated by the HFI for a corresponding transactional synchronization session managed by the HFI of the computing node. Additionally, the HFI is configured to store received data associated with received write transaction that include the transaction identifier in a local buffer of the HFI. Upon receiving a transactional synchronization session termination request, the HFI is configured to initiate a write of the data stored in the local buffer of the HFI to one of the one or more data storage devices of the computing node. Other embodiments are described herein.
摘要:
The present disclosure relates to techniques for determining optimal routing paths for computing devices in a network, including selecting an optimal gateway among a number of available gateways. The techniques include gathering data regarding characteristics of a network, including gateways and network access nodes (NANs) in at least one access network. The characteristics can include, e.g., supported frequency bands, communication protocols, signal-to-noise ratio, power, signal noise and quality, slicing information, and whether a network vender is a standalone network vendor or a non-standalone network vendor. In one aspect, the characteristics are obtained using the Mobile Broadband Interface Model (MBIM). The characteristics can be used by devices in determining routing paths based on requirements of individual flows and/or workflows of individual application instances.
摘要:
A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
摘要:
Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.
摘要:
Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
摘要:
A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要:
Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要:
Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
摘要:
A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.