公开(公告)号：US20070075786A1

公开(公告)日：2007-04-05

申请号：US11473993

申请日：2006-06-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03L7/00

CPC分类号： H03L7/0896 ,  H03L7/0893 ,  H03L7/18 ,  H03L7/193

摘要： A frequency synthesizer includes analog components and digital components. The frequency synthesizer includes at least one shunt regulator that is coupled to a supply rail to provide power to at least one of the digital components. The frequency synthesizer also includes at least one series regulator that is coupled to the supply rail to provide power to at least one of the analog components.

摘要翻译： 频率合成器包括模拟组件和数字组件。 频率合成器包括至少一个并联稳压器，其耦合到电源轨以向至少一个数字组件提供功率。 频率合成器还包括耦合到电源轨的至少一个串联调节器，以向至少一个模拟组件供电。

公开(公告)号：US20060139105A1

公开(公告)日：2006-06-29

申请号：US11023981

申请日：2004-12-28

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0893 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/04

摘要： Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

公开(公告)号：US07750704B2

公开(公告)日：2010-07-06

申请号：US12256800

申请日：2008-10-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03K12/00

CPC分类号： H03L7/0895

摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

摘要翻译： 参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。 整形电路整形周期信号以产生时钟信号。 滤波器位于振荡器和整形电路之间。

公开(公告)号：US20090039935A1

公开(公告)日：2009-02-12

申请号：US12256800

申请日：2008-10-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03K12/00

CPC分类号： H03L7/0895

摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

摘要翻译： 参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。 整形电路整形周期信号以产生时钟信号。 滤波器位于振荡器和整形电路之间。

公开(公告)号：US20060141963A1

公开(公告)日：2006-06-29

申请号：US11024025

申请日：2004-12-28

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H04B1/18

CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/18

摘要： A noise attenuator loop filter for PLL applications that allows a full on-chip integration of the loop filter capacitors, while ensuring a low output clock phase noise (jitter) is disclosed. A voltage attenuator (A) is inserted between the loop filter (passive or active) and the controlled oscillator. The attenuator attenuates the noise coming from the loop filter. In case of a passive RC filter, the series resistor noise power is attenuated by A2 times, allowing the usage of a resistor that is A2 times larger and therefore the loop filter capacitors result A2 times smaller (easy to integrate on-chip). The relatively low value capacitor allows the usage of thick-oxide accumulation-mode MOSFET capacitors that take a reasonable low area, have a good linearity, are isolated from the substrate by the grounded N-well, and have negligible gate leakage current. Several embodiments of the noise attenuator are proposed for different practical applications: clock generation for digital circuits, frequency translation, low or high supply voltage, narrow or wide frequency range, processes with or without isolated well devices, processes with or without polysilicon resistors, and medium or high reference spurs rejection.

摘要翻译： 用于PLL应用的噪声衰减器环路滤波器，其允许环路滤波电容器的完全片上集成，同时确保低输出时钟相位噪声（抖动）。 电压衰减器（A）插入在环路滤波器（无源或有源）和受控振荡器之间。 衰减器衰减来自环路滤波器的噪声。 在无源RC滤波器的情况下，串联电阻噪声功率被衰减了2倍以上，允许使用大于等于2的电阻倍数，因此环路 滤波电容器的结果是小于2倍（容易集成在片上）。 相对低价值的电容器允许使用具有合理的低面积，具有良好线性度的厚氧化物堆积型MOSFET电容器，通过接地的N阱与衬底隔离，并且具有可忽略的栅极漏电流。 针对不同的实际应用提出了噪声衰减器的几个实施例：用于数字电路的时钟产生，频率转换，低或高电源电压，窄或宽频率范围，具有或不具有隔离阱器件的工艺，具有或不具有多晶硅电阻器的工艺，以及 中等或高参考杂散排斥。

公开(公告)号：US20060089114A1

公开(公告)日：2006-04-27

申请号：US11240814

申请日：2005-09-30

申请人： Adrian Maxim ,  Ramin Khoini-Poorfard ,  James Kao

发明人： Adrian Maxim ,  Ramin Khoini-Poorfard ,  James Kao

IPC分类号： H04H1/00 ,  H04B1/18

CPC分类号： H04N7/20 ,  H03D3/006 ,  H03D3/007 ,  H03J1/0066 ,  H03K3/0322 ,  H03L7/18 ,  H04H40/90 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/50 ,  H04N21/4263

摘要： A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.

公开(公告)号：US07599673B2

公开(公告)日：2009-10-06

申请号：US11240814

申请日：2005-09-30

申请人： Adrian Maxim ,  Ramin Khoini-Poorfard ,  James Kao

发明人： Adrian Maxim ,  Ramin Khoini-Poorfard ,  James Kao

IPC分类号： H04B1/18

CPC分类号： H04N7/20 ,  H03D3/006 ,  H03D3/007 ,  H03J1/0066 ,  H03K3/0322 ,  H03L7/18 ,  H04H40/90 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/50 ,  H04N21/4263

摘要： A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.

摘要翻译： 一种技术包括在第一频率范围内接收包括多个信道的信号频谱。 该技术包括接收标识要调谐的至少一个期望信道的选择信号。 该技术包括提供具有与第一频率范围基本相同的第二频率范围的振荡器，并且控制振荡器以产生多个粗调模拟混合信号之一。 信号基本跨越第二频率范围，并且每个信号取决于信号频谱内期望信道的位置。 该技术包括将信号频谱与所选择的粗调模拟混合信号混合以产生粗调谐信号频谱。 该技术包括对粗调谐信号频谱进行数字处理以微调所需信道并产生所需信道的数字基带信号。

公开(公告)号：US07095287B2

公开(公告)日：2006-08-22

申请号：US11023981

申请日：2004-12-28

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03L7/06 ,  H03L7/08

CPC分类号： H03L7/093 ,  H03L7/0893 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/04

摘要： Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

摘要翻译： 公开了针对环路带宽和阻尼因子提供过程，温度和分频器模数独立性的锁相环电路（PLL）的几种开环校准技术。 介绍了两类开环技术。 第一种方法仅使用来自振荡器的输出频率的单次测量，并调整执行环路带宽和阻尼因子同时校准的单个PLL环路元件。 对于振荡器控制信号的给定值测量输出频率，并且调整电荷泵电流，使得其消除振荡器增益的过程变化。 第二种方法使用两个单独的和正交的校准步骤，它们都基于当将已知的激励施加到开环信号路径时来自振荡器的输出频率的测量。 在第一步中，通过在进入相位频率检测器的两个时钟之间施加恒定相移时，基于正向通路增益的测量来调整电荷泵电流，同时积分路径保持为 恒定值。 在第二步中，通过调整积分环路滤波电容器的值，通过调整积分环路滤波电容器的值，通过与积分电容器值成比例的电压激励时的振荡器输出频率的测量，同时比例控制​​分量为零，校准阻尼系数。

公开(公告)号：US20070075793A1

公开(公告)日：2007-04-05

申请号：US11473742

申请日：2006-06-23

申请人： Adrian Maxim ,  James Kao

发明人： Adrian Maxim ,  James Kao

IPC分类号： H03B1/00

CPC分类号： H03L7/0895

摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

摘要翻译： 参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。 整形电路整形周期信号以产生时钟信号。 滤波器位于振荡器和整形电路之间。

公开(公告)号：US07773968B2

公开(公告)日：2010-08-10

申请号：US11565487

申请日：2006-11-30

申请人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

发明人： Adrian Maxim ,  Charles D. Thompson ,  Mitchell Reid

IPC分类号： H04B1/10

CPC分类号： H04B1/28 ,  H04B1/001 ,  H04B1/0039

摘要： A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.

摘要翻译： 接收器（1300）包括混合数模转换器（DAC）（1306），直接数字频率合成器（DDFS）（132A）和接口（134D）。 混合DAC（1306）包括射频（RF）跨导部分（1308）和切换部分（1310）。 RF跨导部分（1308）包括用于接收RF信号的输入端和用于提供RF电流信号的输出端。 开关部分（1310）耦合到RF跨导部分（1308），并且包括用于接收与数字本地振荡器（LO）信号相关联的位的输入和被配置为提供模拟输出信号的输出。 DDFS（132A）包括被配置为将与数字LO信号相关联的位提供给切换部分（1310）的输入的输出。 接口（134D）耦合到DDFS（132A），并且被配置为将由DDFS（132A）提供的位与第一时钟信号对准。