公开(公告)号：US09209278B2

公开(公告)日：2015-12-08

申请号：US14195712

申请日：2014-03-03

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Daniel Tang ,  Tzu-Shih Yen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/165 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract translation: 形成具有在源极区和漏极区之间具有源极区，漏极区和沟道区的鳍的finFET。 翅片在半导体晶片上蚀刻。 形成具有与沟道区域直接接触的绝缘层和与绝缘层直接接触的导电栅极材料的栅极堆叠。 蚀刻源极和漏极区域，离开鳍片的沟道区域。 外延半导体在与源极和漏极区相邻的沟道区的侧面生长以形成源外延区和漏极外延区。 源极和漏极外延区域在生长外延半导体的同时原位掺杂。

公开(公告)号：US09006065B2

公开(公告)日：2015-04-14

申请号：US13648127

申请日：2012-10-09

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Tzu-Shih Yen ,  Daniel Tang ,  Tsungnan Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L27/12 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/2236 ,  H01L29/66803 ,  H01L29/785

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract translation: 在等离子体掺杂非平面半导体器件中，获得其上形成有非平面半导体体的衬底。 具有非平面半导体本体的基板可以放置在室中。 等离子体可以在室中形成，等离子体可以含有掺杂离子。 可以产生第一偏置电压以将掺杂剂离子注入到非平面半导体本体的区域中。 可以产生第二偏置电压以将掺杂剂离子注入到相同的区域中。 在一个示例中，第一偏置电压和第二偏置电压可以不同。