公开(公告)号：US20240329838A1

公开(公告)日：2024-10-03

申请号：US18129300

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D. Willey

IPC: G06F3/06 ,  G06F1/12

CPC classification number: G06F3/0611 ,  G06F1/12 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

Abstract: A data processing system includes a data processor having a memory controller, and a memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.

公开(公告)号：US20240111618A1

公开(公告)日：2024-04-04

申请号：US17956542

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D. Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman ,  Ramon Mangaser

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073

Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.

公开(公告)号：US11996848B1

公开(公告)日：2024-05-28

申请号：US17979622

申请日：2022-11-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D. Willey ,  Karthik Gopalakrishnan

IPC: H03K5/135 ,  H03K5/14 ,  H03K7/06

CPC classification number: H03K5/135 ,  H03K5/14 ,  H03K7/06

Abstract: The disclosed computer-implemented method includes providing, by a reference clock circuit, a clock signal for a clock-triggered element triggered by the clock signal and modulating, by a frequency modulation circuit, a frequency of the clock signal. The method also includes inserting, by a phase compensation circuit, a phase compensation offset to the modulated clock signal in a manner that compensates for a phase error produced by modulating the frequency of the clock signal. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240192858A1

公开(公告)日：2024-06-13

申请号：US18079239

申请日：2022-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D. Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0673

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.