公开(公告)号：US20210409020A1

公开(公告)日：2021-12-30

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K17/687 ,  H03K19/0948 ,  H03K19/0185 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165 ,  G05F3/20

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

公开(公告)号：US11418189B2

公开(公告)日：2022-08-16

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/0948 ,  H03K17/687 ,  H03K19/0185 ,  G05F3/20 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

公开(公告)号：US11418187B1

公开(公告)日：2022-08-16

申请号：US17486425

申请日：2021-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Sahu ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K5/22 ,  H03K17/22 ,  H03K5/24 ,  H03K3/3565 ,  G06F1/24 ,  G06F1/28

Abstract: A power supply detection circuit for an integrated circuit (IC) includes a reference voltage circuit and a comparator circuit. The reference voltage circuit produces a reference voltage from the supply voltage at a reference voltage node. The comparator circuit includes a first p-type metal oxide semiconductor (PMOS) transistor with a source coupled to a positive supply terminal, a gate receiving the reference voltage, and a drain connected to a comparator output terminal. A first n-type metal oxide semiconductor (NMOS) transistor has a drain connected to the comparator output terminal, a source connected to the negative supply terminal, and a gate receiving a second voltage that varies relative to the supply voltage. A second PMOS transistor has a source coupled to the positive supply terminal, a gate connected to the reference voltage node, and a drain providing the second voltage and coupled to a filter.