公开(公告)号：US09046574B2

公开(公告)日：2015-06-02

申请号：US13687837

申请日：2012-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。

公开(公告)号：US20140237312A1

公开(公告)日：2014-08-21

申请号：US13773501

申请日：2013-02-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Atchyuth K. Gorti ,  Aditya Jagirdar ,  Bikash Kumar Agarwal ,  Eric Quinnell

IPC: G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract translation: 报告集成电路设备的扫描预热方法。 一种这样的方法可以包括以等于测试时钟频率的扫描时钟第一频率将扫描测试激励加载并从集成电路器件的第一组逻辑元件卸载扫描测试响应; 通过扫描预热单元将扫描时钟从第一频率调整到第二频率，其中扫描时钟第二频率等于系统时钟频率; 并且以扫描时钟第二频率通过移位逻辑捕获扫描测试响应。 我们还会报告包含配置为实现该方法的组件以及这些处理器的制造的处理器。 这些方法及其实现可以减少在测试集成电路器件的逻辑元件时通常发生的di / dt事件。

公开(公告)号：US20140132291A1

公开(公告)日：2014-05-15

申请号：US13675704

申请日：2012-11-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Archana Somachudan ,  Atchyuth K. Gorti

IPC: G01R31/3187

CPC classification number: G01R31/3187 ,  G01R31/31724

Abstract: A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals.

Abstract translation: 具有内置自检（BIST）能力的电路包括主BIST控制器，多个从BIST控制器和收集器。 主控制器控制器响应于主恢复输入信号发出测试指令。 多个从BIST控制器耦合到主BIST控制器。 每个从BIST控制器适于响应于测试指令对功能电路进行测试，并在测试结束时提供恢复信号。 在主BIST控制器发出测试指令之后，集线器从多个从BIST控制器中的每一个接收相应的恢复信号，随后响应于所有相应的恢复信号的激活而提供主恢复信号。

公开(公告)号：US09024650B2

公开(公告)日：2015-05-05

申请号：US13675704

申请日：2012-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Archana Somachudan ,  Atchyuth K. Gorti

IPC: G01R31/3187 ,  G01R31/317

CPC classification number: G01R31/3187 ,  G01R31/31724

Abstract: A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals.

Abstract translation: 具有内置自检（BIST）能力的电路包括主BIST控制器，多个从BIST控制器和收集器。 主控制器控制器响应于主恢复输入信号发出测试指令。 多个从BIST控制器耦合到主BIST控制器。 每个从BIST控制器适于响应于测试指令对功能电路进行测试，并在测试结束时提供恢复信号。 在主BIST控制器发出测试指令之后，集线器从多个从BIST控制器中的每一个接收相应的恢复信号，随后响应于所有相应的恢复信号的激活而提供主恢复信号。

公开(公告)号：US20140173345A1

公开(公告)日：2014-06-19

申请号：US13718944

申请日：2012-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Atchyuth K. Gorti ,  Archana Somachudan

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G11C29/16

Abstract: A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

Abstract translation: 描述了具有主器件和一个或多个从器件MBIST控制器的半导体器件（例如多处理器）的可扩展的可重新配置的内存自检（MBIST）架构。 MBIST架构包括与主MBIST控制器以环形连接的多个MBISTDP接口。 每个MBISTDP接口连接至少一个从控制器，用于通过环从Master MBIST控制器转发测试信息。 测试信息包括测试数据，地址和MBIST测试命令。 每个MBISTDP接口将信息转发到连接到其上的从属控制器，并转发到环上的下一个MBISTDP接口。 测试结果数据从环上的MBISTDP接口发送回主MBIST控制器。

公开(公告)号：US20140149813A1

公开(公告)日：2014-05-29

申请号：US13687837

申请日：2012-11-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。