公开(公告)号：US11657892B1

公开(公告)日：2023-05-23

申请号：US17561115

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Joel Thornton Irby ,  Grady L. Giles

IPC: G11C7/10 ,  G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1036 ,  G11C7/1087 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/1202

Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

公开(公告)号：US09046574B2

公开(公告)日：2015-06-02

申请号：US13687837

申请日：2012-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。

公开(公告)号：US12100464B2

公开(公告)日：2024-09-24

申请号：US18302510

申请日：2023-04-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Joel Thornton Irby ,  Grady L. Giles

IPC: G11C7/10 ,  G11C29/12 ,  G11C29/44 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C7/1012 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1087 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/1202

Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

公开(公告)号：US20140149813A1

公开(公告)日：2014-05-29

申请号：US13687837

申请日：2012-11-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。