公开(公告)号：US20240329135A1

公开(公告)日：2024-10-03

申请号：US18193973

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James A. Wingfield

IPC: G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318544

Abstract: A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network, setting the enable configuration for the one or more multi-cycle paths, and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.

公开(公告)号：US20210407617A1

公开(公告)日：2021-12-30

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US20140149813A1

公开(公告)日：2014-05-29

申请号：US13687837

申请日：2012-11-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。

公开(公告)号：US11264115B2

公开(公告)日：2022-03-01

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US09046574B2

公开(公告)日：2015-06-02

申请号：US13687837

申请日：2012-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Grady L. Giles ,  James A. Wingfield ,  Atchyuth K. Gorti

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318544 ,  G01R31/318555

Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Abstract translation: 用于功能电路的测试电路包括耦合到功能电路的扫描链和耦合到扫描链的控制器，用于控制扫描链将测试图案扫描到扫描链中，并且随后和重复地进行多个 时间将测试模式发送到功能电路，将测试数据捕获到扫描链中，并恢复扫描链中的测试模式，以便后续启动。