公开(公告)号：US20240088098A1

公开(公告)日：2024-03-14

申请号：US18199837

申请日：2023-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Niti MADAN ,  Michael IGNATOWSKI ,  Hyung-Dong LEE

IPC: H01L25/065 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L2225/06503

Abstract: Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-volatile memory (NVM) technologies are in a memory stack with low temperature memory dies, such as those having volatile memory technologies. In some cases, the high temperature memory technologies could be used together, in some cases, on the same IC die as logic circuitry. In one example, a memory stack is provided that include a first memory IC die having high temperature memory circuitry, such as non-volatile memory, stacked below a second memory IC die. The second memory IC die has high temperature memory circuitry, such as volatile memory circuitry.

公开(公告)号：US20220092724A1

公开(公告)日：2022-03-24

申请号：US17030024

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niti MADAN ,  Michael L. CHU ,  Ashwin AJI

IPC: G06T1/60 ,  G06F9/50 ,  G06F3/06 ,  G06T1/20

Abstract: One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding program code are used to determine the memory access characteristics. The memory access characteristics can also be determined by monitoring memory access requests, measuring a cache miss rate or a row buffer miss rate for the monitored memory access requests, and determining the memory access characteristics based on the cache miss rate or the row buffer miss rate.

公开(公告)号：US20240087632A1

公开(公告)日：2024-03-14

申请号：US18216501

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Michael IGNATOWSKI ,  Niti MADAN

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2275

Abstract: A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.