公开(公告)号：US20140189700A1

公开(公告)日：2014-07-03

申请号：US13727808

申请日：2012-12-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Douglas R. Williams ,  Vydhyanathan Kalyanasundharam ,  Marius Evers ,  Michael K. Fertig

IPC: G06F9/50

CPC classification number: G06F13/1642 ,  G06F13/4027

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.

Abstract translation: 处理器使用令牌方案来管理处理器核心在处理器的北桥处可能具有的一组处理器核心的每个存储器访问请求的最大数量。 为了实施该方案，北桥向每个处理器核心发出最少的令牌数，并保留了一些令牌。 响应于确定给定的处理器核心正在产生高水平的存储器访问活动，北桥向处理器核心发出一些保留令牌。 响应于确定不可能继续生成大量的存储器访问请求，处理器核心将保留令牌返回到北桥，使得保留令牌可用于发布到另一个处理器核心。

公开(公告)号：US10896044B2

公开(公告)日：2021-01-19

申请号：US16014715

申请日：2018-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  Dhanaraj Bapurao Tavare ,  Ashok Tirupathy Venkatachar ,  Arunachalam Annamalai ,  Donald A. Priore ,  Douglas R. Williams

IPC: G06F9/38

Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

公开(公告)号：US20190391813A1

公开(公告)日：2019-12-26

申请号：US16014715

申请日：2018-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  Dhanaraj Bapurao Tavare ,  Ashok Tirupathy Venkatachar ,  Arunachalam Annamalai ,  Donald A. Priore ,  Douglas R. Williams

IPC: G06F9/38

Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

公开(公告)号：US09697146B2

公开(公告)日：2017-07-04

申请号：US13727808

申请日：2012-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas R. Williams ,  Vydhyanathan Kalyanasundharam ,  Marius Evers ,  Michael K. Fertig

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/4027

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.