公开(公告)号：US12210767B2

公开(公告)日：2025-01-28

申请号：US17032217

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gregg Donley ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam ,  Bryan Broussard

IPC: G06F3/06

Abstract: A system for combining write transactions of a large write includes a processor including at least a first die and a second die, and a link coupling the first die and the second die. When a link interface on one die transmits packets to the other die over the link, the link interface identifies, from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction. The link interface determines whether two or more candidate write transactions are combinable based on a set of conditions. When two or more candidate write transaction are combinable, the link interface combines the candidate write transactions into a single combined write transaction and transmits the combined write transaction. A link interface on the receiving die decodes the combined write transaction and iteratively regenerates the individual write transactions using control information in the combined write transaction.

公开(公告)号：US12167102B2

公开(公告)日：2024-12-10

申请号：US16138117

申请日：2018-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Joe G. Cruz ,  Eric Christopher Morton ,  Alan Dodson Smith

IPC: H04W72/00 ,  H04L12/18 ,  H04L12/50 ,  H04L12/54 ,  H04L45/021 ,  H04L45/745 ,  H04L47/6275 ,  H04L49/101 ,  H04L65/1101 ,  H04L65/611 ,  H04N19/164 ,  H04N19/169 ,  H04N21/6405

Abstract: Systems, apparatuses, and methods for processing multi-cast messages are disclosed. A system includes at least one or more processing units, one or more memory controllers, and a communication fabric coupled to the processing unit(s) and the memory controller(s). The communication fabric includes a plurality of crossbars which connect various agents within the system. When a multi-cast message is received by a crossbar, the crossbar extracts a message type indicator and a recipient type indicator from the message. The crossbar uses the message type indicator to determine which set of masks to lookup using the recipient type indicator. Then, the crossbar determines which one or more masks to extract from the selected set of masks based on values of the recipient type indicator. The crossbar combines the one or more masks with a multi-cast route to create a port vector for determining on which ports to forward the multi-cast message.

公开(公告)号：US12158845B2

公开(公告)日：2024-12-03

申请号：US17721809

申请日：2022-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

IPC: G06F12/0817

Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

公开(公告)号：US12093689B2

公开(公告)日：2024-09-17

申请号：US17032301

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  John Petry ,  Chen-Ping Yang ,  Rostyslav Kyrychynskyi ,  Vydhyanathan Kalyanasundharam

IPC: G06F11/14 ,  G06F1/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/46 ,  G06F13/40

CPC classification number: G06F9/3005 ,  G06F9/3877 ,  G06F9/4418 ,  G06F9/463 ,  G06F13/4022

Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

公开(公告)号：US20240220320A1

公开(公告)日：2024-07-04

申请号：US18091681

申请日：2022-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Mahesh UdayKumar Wagh ,  Francisco L. Duran ,  Vydhyanathan Kalyanasundharam

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/5016 ,  G06F9/544

Abstract: An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable media are also disclosed.

公开(公告)号：US20230341922A1

公开(公告)日：2023-10-26

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US20230315657A1

公开(公告)日：2023-10-05

申请号：US17710413

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Bryan Broussard ,  Pravesh Gupta ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/40

Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.

公开(公告)号：US20230195642A1

公开(公告)日：2023-06-22

申请号：US17556257

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  John Wuu ,  Chintan S. Patel

IPC: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/1668

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

公开(公告)号：US20220404978A1

公开(公告)日：2022-12-22

申请号：US17895357

申请日：2022-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US20210406177A1

公开(公告)日：2021-12-30

申请号：US17033287

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien

IPC: G06F12/0817

Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.