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    PRESERVING MEMORY ORDERING BETWEEN OFFLOADED INSTRUCTIONS AND NON-OFFLOADED INSTRUCTIONS
    1.
    发明公开
    PRESERVING MEMORY ORDERING BETWEEN OFFLOADED INSTRUCTIONS AND NON-OFFLOADED INSTRUCTIONS 审中-公开

    公开(公告)号：US20230244492A1

    公开(公告)日：2023-08-03

    申请号：US18298723

    申请日：2023-04-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/52

    CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/522 ,  G06F9/3877

    Abstract: Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

    MANAGING CACHED DATA USED BY PROCESSING-IN-MEMORY INSTRUCTIONS
    2.
    发明申请
    MANAGING CACHED DATA USED BY PROCESSING-IN-MEMORY INSTRUCTIONS 有权

    公开(公告)号：US20220188233A1

    公开(公告)日：2022-06-16

    申请号：US17473242

    申请日：2021-09-13

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JOHN KALAMATIANOS ,  JAGADISH B. KOTRA ,  GAGANDEEP PANWAR

    IPC: G06F12/0817

    Abstract: A system-on-chip configured for eager invalidation and flushing of cached data used by PIM (Processing-in-Memory) instructions includes: one or more processor cores; one or more caches and an I/O (input/output) die comprising logic to: receive a cache probe request, wherein the cache probe request including a physical memory address associated with a PIM instruction, and the PIM instruction is to be offloaded to a PIM device for execution; and issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device.

    ADDRESS-BASED FILTERING FOR LOAD/STORE SPECULATION
    3.
    发明申请
    ADDRESS-BASED FILTERING FOR LOAD/STORE SPECULATION 有权

    公开(公告)号：US20210117195A1

    公开(公告)日：2021-04-22

    申请号：US16658474

    申请日：2019-10-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JOHN KALAMATIANOS ,  KRISHNAN V. RAMANI ,  SUSUMU MASHIMO

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/35

    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

    OFFLOADING COMPUTATIONS FROM A PROCESSOR TO REMOTE EXECUTION LOGIC
    5.
    发明申请
    OFFLOADING COMPUTATIONS FROM A PROCESSOR TO REMOTE EXECUTION LOGIC 有权

    公开(公告)号：US20220206855A1

    公开(公告)日：2022-06-30

    申请号：US17136767

    申请日：2020-12-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： NAGADASTAGIRI REDDY CHALLAPALLE ,  JAGADISH B. KOTRA ,  JOHN KALAMATIANOS

    IPC: G06F9/50

    Abstract: Offloading computations from a processor to remote execution logic is disclosed. Offload instructions for remote execution on a remote device are dispatched in the form of processor instructions like conventional instructions. In the processor, an offload instruction is inserted in an offload queue. The offload instruction may be inserted at the dispatch stage or the retire stage of the processor pipeline. Metadata for the offload instruction is added to the offload instruction in the offload queue. After retirement of the offload instruction, the processor transmits an offload request generated from the offload instruction.

    PUSHED PREFETCHING IN A MEMORY HIERARCHY
    8.
    发明公开
    PUSHED PREFETCHING IN A MEMORY HIERARCHY 审中-公开

    公开(公告)号：US20240111678A1

    公开(公告)日：2024-04-04

    申请号：US17958120

    申请日：2022-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS ,  PAUL MOYER ,  GABRIEL H. LOH

    IPC: G06F12/0862 ,  G06F12/0811

    CPC classification number: G06F12/0862 ,  G06F12/0811

    Abstract: Systems and methods for pushed prefetching include: multiple core complexes, each core complex having multiple cores and multiple caches, the multiple caches configured in a memory hierarchy with multiple levels; an interconnect device coupling the core complexes to each other and coupling the core complexes to shared memory, the shared memory at a lower level of the memory hierarchy than the multiple caches; and a push-based prefetcher having logic to: monitor memory traffic between caches of a first level of the memory hierarchy and the shared memory; and based on the monitoring, initiate a prefetch of data to a cache of the first level of the memory hierarchy.

    LEVERAGING PROCESSING-IN-MEMORY (PIM) RESOURCES TO EXPEDITE NON-PIM INSTRUCTIONS EXECUTED ON A HOST
    9.
    发明公开
    LEVERAGING PROCESSING-IN-MEMORY (PIM) RESOURCES TO EXPEDITE NON-PIM INSTRUCTIONS EXECUTED ON A HOST 审中-公开

    公开(公告)号：US20230205693A1

    公开(公告)日：2023-06-29

    申请号：US17564155

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS ,  YASUKO ECKERT ,  YONGHAE KIM

    IPC: G06F12/0811

    CPC classification number: G06F12/0811

    Abstract: Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to the first memory location. In another implementation, a memory controller identifies a first memory location associated with a first read instruction, where the first read instruction is not a processing-in-memory (PIM) instruction. The memory controller identifies that a PIM register is associated with the first memory location. The memory controller then reads, in response to the first read instruction, first data from the PIM register.

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