公开(公告)号：US20240071903A1

公开(公告)日：2024-02-29

申请号：US17896616

申请日：2022-08-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GABRIEL H. LOH ,  RAJA SWAMINATHAN ,  RAHUL AGARWAL

IPC: H01L23/522 ,  H01L23/16 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/16 ,  H01L23/528

Abstract: A semiconductor package assembly includes a die having a front surface and a back surface opposite to and parallel to the front surface. A first portion of a front surface of an interconnect die is coupled to a portion of the back surface of the die. The interconnect die includes a connectivity region that is coupled to one or more through-die vias in the die through the back surface of the die. A spacer component is coupled to a second portion of the front surface of the interconnect die. The spacer component includes conductive connections, with one or more of the conductive connections are coupled to the conductive pathways of the connectivity region of the interconnect die.

公开(公告)号：US20240111678A1

公开(公告)日：2024-04-04

申请号：US17958120

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS ,  PAUL MOYER ,  GABRIEL H. LOH

IPC: G06F12/0862 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F12/0811

Abstract: Systems and methods for pushed prefetching include: multiple core complexes, each core complex having multiple cores and multiple caches, the multiple caches configured in a memory hierarchy with multiple levels; an interconnect device coupling the core complexes to each other and coupling the core complexes to shared memory, the shared memory at a lower level of the memory hierarchy than the multiple caches; and a push-based prefetcher having logic to: monitor memory traffic between caches of a first level of the memory hierarchy and the shared memory; and based on the monitoring, initiate a prefetch of data to a cache of the first level of the memory hierarchy.

公开(公告)号：US20190294412A1

公开(公告)日：2019-09-26

申请号：US15933229

申请日：2018-03-22

Applicant: Advanced Micro Devices, Inc.

Inventor： GABRIEL H. LOH

IPC: G06F7/499 ,  G06F7/58

Abstract: Techniques and circuits are provided for stochastic rounding. In an embodiment, a circuit includes carry-save adder (CSA) logic having three or more CSA inputs, a CSA sum output, and a CSA carry output. One of the three or more CSA inputs is presented with a random number value, while other CSA inputs are presented with input values to be summed. The circuit further includes adder logic having adder inputs and a sum output. The CSA carry output of the CSA logic is coupled with one of the adder inputs of the adder logic, and the CSA sum output of the CSA logic is coupled with another input of the adder inputs of the adder logic. A particular number of most significant bits of the sum output of the adder logic represent a stochastically rounded sum of the input values.

公开(公告)号：US20240203736A1

公开(公告)日：2024-06-20

申请号：US18065816

申请日：2022-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GABRIEL H. LOH ,  TODD DAVID BASSO ,  STEVEN TU ,  JOSHUA A. HORT ,  CHIA-KEN LEONG ,  BENJAMIN BEKER ,  ANWAR P. KASHEM

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/02697 ,  H01L21/6835

Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.

公开(公告)号：US20240113004A1

公开(公告)日：2024-04-04

申请号：US17957444

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GABRIEL H. LOH ,  ERIC J. CHAPMAN ,  RAJA SWAMINATHAN

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9211

Abstract: A semiconductor package assembly includes a package interface. An interposer die has a first surface and a second surface opposite to the first surface, where the first surface of the interposer is die positioned on the package interface. The interposer die includes a plurality of conductive connections between the first surface and second surface. A chiplet includes a connectivity region having conductive pathways, with a first portion of the connectivity region coupled to a conductive connection of the interposer die and a second portion of the connectivity region cantilevered from the interposer die.

公开(公告)号：US20240071940A1

公开(公告)日：2024-02-29

申请号：US18505187

申请日：2023-11-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  MICHAEL S. ALFANO ,  GABRIEL H. LOH ,  ALAN D. SMITH ,  GABRIEL WONG ,  MICHAEL MANTOR

IPC: H01L23/538 ,  H01L21/50 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.