公开(公告)号：US20150019823A1

公开(公告)日：2015-01-15

申请号：US13942291

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Junli Gu ,  Yi Xu

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/123 ,  G06F12/126

Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.

Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 高速缓存阵列具有多个条目。 缓存控制器耦合到高速缓存阵列。 高速缓存控制器根据高速缓存替换策略从高速缓存阵列中排除条目。 高速缓存控制器通过从第一高速缓存行产生对修改数据的回写请求，从高速缓冲存储器阵列中驱除第一高速缓存行，并且随后如果第二高速缓存行即将满足第二高速缓存行，则从第二高速缓存行生成对修改数据的回写请求 高速缓存替换策略并将来自公共位置的数据存储为第一高速缓存行。

公开(公告)号：US20160098275A1

公开(公告)日：2016-04-07

申请号：US13976905

申请日：2013-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yuan Xie ,  Junli Gu

IPC: G06F9/30

CPC classification number: G06F9/30083 ,  G06F8/4432 ,  G06F9/30087 ,  G06F9/30149 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

Abstract translation: 描述了一种用于通过确定处理器的热约束来编译在具有多个功能单元的处理器中执行的指令代码的方法的实施例，并且将包括实际指令和一个或多个无操作（NOP）指令的指令字定义为 在单个时钟周期内由功能单元执行，其中在多个连续时钟周期执行的多个NOP指令被配置为在执行指令代码期间防止超过热约束。

公开(公告)号：US09317448B2

公开(公告)日：2016-04-19

申请号：US13953835

申请日：2013-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Xie Yuan ,  Junli Gu ,  Yi Xu ,  ShuChang Shan ,  Shuai Mu ,  Ting Cao

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0804 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1024

Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.

Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。

公开(公告)号：US20150039836A1

公开(公告)日：2015-02-05

申请号：US13953835

申请日：2013-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Xie Yuan ,  Junli Gu ,  Yi Xu ,  ShuChang Shan ,  Shuai Mu ,  Ting Cao

IPC: G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0804 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1024

Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.

Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。

公开(公告)号：US09792228B2

公开(公告)日：2017-10-17

申请号：US14229404

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/127 ,  G06F12/121

CPC classification number: G06F12/127 ,  G06F12/121 ,  G06F2212/222

Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.

公开(公告)号：US20150100739A1

公开(公告)日：2015-04-09

申请号：US14229404

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe WANG ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/127 ,  G06F12/121 ,  G06F2212/222

Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.

Abstract translation: 提供了用于写入非易失性高速缓冲存储器的方法，系统和计算机可读介质。 该方法保持与一组存储器位置相关联的写入计数。 然后，该方法基于写入计数的值来选择高速缓存替换策略，并且使用所选择的高速缓存替换策略来选择用于写入数据的集合内的块。 所选择的高速缓存替换策略可以引入随机选择。

公开(公告)号：US09767043B2

公开(公告)日：2017-09-19

申请号：US14229420

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/126 ,  G06F3/06 ,  G06F12/00 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/126 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0628 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0674 ,  G06F3/0676 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/12 ,  G06F12/121

Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.

公开(公告)号：US09639359B2

公开(公告)日：2017-05-02

申请号：US13976905

申请日：2013-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yuan Xie ,  Junli Gu

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/30083 ,  G06F8/4432 ,  G06F9/30087 ,  G06F9/30149 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

公开(公告)号：US09552301B2

公开(公告)日：2017-01-24

申请号：US13942291

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Junli Gu ,  Yi Xu

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/123 ,  G06F12/126

Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.

Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 高速缓存阵列具有多个条目。 缓存控制器耦合到高速缓存阵列。 高速缓存控制器根据高速缓存替换策略从高速缓存阵列中排除条目。 高速缓存控制器通过从第一高速缓存行产生对修改数据的回写请求，从高速缓冲存储器阵列中驱除第一高速缓存行，并且随后如果第二高速缓存行即将满足第二高速缓存行，则从第二高速缓存行生成对修改数据的回写请求 高速缓存替换策略并将来自公共位置的数据存储为第一高速缓存行。