公开(公告)号：US20230208424A1

公开(公告)日：2023-06-29

申请号：US17563980

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Deepesh John

IPC: H03K19/096 ,  H03K19/0185 ,  H03K3/012

CPC classification number: H03K19/0963 ,  H03K19/018521 ,  H03K3/012

Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.

公开(公告)号：US11095274B1

公开(公告)日：2021-08-17

申请号：US17032530

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nur Mohammad Baksh ,  Michael Q. Co

IPC: H03K3/0233 ,  H03K3/037 ,  H03K3/3562

Abstract: A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal.

公开(公告)号：US12160238B2

公开(公告)日：2024-12-03

申请号：US17563980

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Deepesh John

IPC: H03K19/096 ,  H03K3/012 ,  H03K19/0185

Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.

公开(公告)号：US11789075B1

公开(公告)日：2023-10-17

申请号：US17853409

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Michael Q. Co ,  Vibhor Mittal ,  Kedar Karthykeyan

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318552

Abstract: A method includes generating a functional clock signal, a scan clock signal, and a delayed clock signal based on a control clock signal and a scan enable signal. The method includes precharging or predischarging a differential pair of nodes in a first latch using the delayed clock signal and a voltage on a first power supply node and controlling a second latch using the delayed clock signal. The method includes latching data input by the first latch using the functional clock signal in a functional mode of operation and latching scan data by the first latch using the scan clock signal in a scan mode of operation.