公开(公告)号：US12056522B2

公开(公告)日：2024-08-06

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/44 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US20230161618A1

公开(公告)日：2023-05-25

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US11042495B2

公开(公告)日：2021-06-22

申请号：US16578165

申请日：2019-09-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F13/24 ,  G06F9/455 ,  G06F13/16

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

公开(公告)号：US20250004949A1

公开(公告)日：2025-01-02

申请号：US18217291

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Paul Blinzer ,  Anthony Asaro ,  Nippon HarshadKumar Raval ,  Anthony Thomas Gutierrez ,  Leopold Grinberg ,  Millind Mittal ,  Samuel Richard Bayliss

IPC: G06F12/1009 ,  G06F12/14

Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

公开(公告)号：US10909053B2

公开(公告)日：2021-02-02

申请号：US16423077

申请日：2019-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F9/455 ,  G06F12/1009 ,  G06F12/02 ,  G06F12/0875 ,  G06F13/16

Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

公开(公告)号：US09239804B2

公开(公告)日：2016-01-19

申请号：US14045701

申请日：2013-10-03

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew Kegel ,  Jimshed Mirza ,  Paul Blinzer ,  Philip Ng

IPC: G06F11/07 ,  G06F13/00 ,  G06F12/10 ,  G06F12/00 ,  G06F13/38

CPC classification number: G06F13/00 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.

Abstract translation: 提供了一种在计算机系统中管理来自外围设备的请求的系统和方法。 在系统和方法中，输入/输出存储器管理单元（IOMMU）从外设接收外围寻呼请求（PPR）。 响应于满足关于PPR日志的可用容量的标准的确定，向外设发送完成消息，指示PPR完成并且PPR被丢弃，而不在PPR日志中排队PPR。

公开(公告)号：US20250021379A1

公开(公告)日：2025-01-16

申请号：US18780862

申请日：2024-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US20250004828A1

公开(公告)日：2025-01-02

申请号：US18216314

申请日：2023-06-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  XILINX, INC.

Inventor： Mark Unruh Wyse ,  Anthony Thomas Gutierrez ,  Paul Blinzer ,  Samuel Richard Bayliss

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor employs a hardware signal monitor to manage signaling for accelerators. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.

公开(公告)号：US12117933B2

公开(公告)日：2024-10-15

申请号：US17117033

申请日：2020-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer

IPC: G06F12/06 ,  G09G5/36

CPC classification number: G06F12/0646 ,  G09G5/363 ,  G06F2212/1008 ,  G09G2360/08 ,  G09G2360/18

Abstract: A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.

公开(公告)号：US20180181341A1

公开(公告)日：2018-06-28

申请号：US15389908

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0683 ,  G06F12/10 ,  G06F2212/65

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.