公开(公告)号：US20140181537A1

公开(公告)日：2014-06-26

申请号：US13724271

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srilatha Manne ,  Rajagopalan Desikan ,  Sanjay Pant ,  Youngtaek Kim

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器内核和电源控制器。 每个数据处理器内核具有用于接收时钟信号的第一输入端，用于接收电源电压的第二输入端和用于提供空闲信号的输出端。 功率控制器耦合到每个数据处理器核心，用于向每个数据处理器核提供时钟信号和电源电压。 功率控制器根据从数据处理器核心接收到的空闲信号的数量，向时钟信号和电源电压提供至少一个数据处理器核心中的一个。

公开(公告)号：US09223383B2

公开(公告)日：2015-12-29

申请号：US13724271

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne ,  Rajagopalan Desikan ,  Sanjay Pant ,  Youngtaek Kim

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器内核和电源控制器。 每个数据处理器内核具有用于接收时钟信号的第一输入端，用于接收电源电压的第二输入端和用于提供空闲信号的输出端。 功率控制器耦合到每个数据处理器核心，用于向每个数据处理器核提供时钟信号和电源电压。 功率控制器根据从数据处理器核心接收到的空闲信号的数量，向时钟信号和电源电压提供至少一个数据处理器核心中的一个。